expand names of SP status flags
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@ -17,13 +17,13 @@ constant SP_PC($00) // $04080000..$04080003 SP: PC Register
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constant SP_IBIST_REG($04) // $04080004..$04080007 SP: IMEM BIST Register
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// SP_STATUS Read Flags:
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constant SP_HLT($0001) // Halt
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constant SP_BRK($0002) // Break
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constant SP_BSY($0004) // DMA Busy
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constant SP_FUL($0008) // DMA Full
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constant SP_IOF($0010) // IO Full
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constant SP_STP($0020) // Single Step
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constant SP_IOB($0040) // Interrupt On Break
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constant SP_HALT($0001)
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constant SP_BREAK($0002)
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constant SP_BUSY($0004) // DMA busy
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constant SP_FULL($0008) // DMA full
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constant SP_IO_FULL($0010)
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constant SP_SINGLE_STEP($0020)
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constant SP_INT_ON_BREAK($0040) // Interrupt On Break
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constant SP_SG0($0080) // Signal 0 Set
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constant SP_SG1($0100) // Signal 1 Set
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constant SP_SG2($0200) // Signal 2 Set
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@ -34,15 +34,15 @@ constant SP_SG6($2000) // Signal 6 Set
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constant SP_SG7($4000) // Signal 7 Set
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// SP_STATUS Write Flags:
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constant SP_HLT_CLR($00000001) // Clear Halt
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constant SP_HLT_SET($00000002) // Set Halt
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constant SP_BRK_CLR($00000004) // Clear Broke
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constant SP_HALT_CLR($00000001)
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constant SP_HALT_SET($00000002)
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constant SP_BREAK_CLR($00000004) // Clear Broke
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constant SP_INT_CLR($00000008) // Clear Interrupt
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constant SP_INT_SET($00000010) // Set Interrupt
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constant SP_STP_CLR($00000020) // Clear Single Step
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constant SP_STP_SET($00000040) // Set Single Step
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constant SP_IOB_CLR($00000080) // Clear Interrupt On Break
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constant SP_IOB_SET($00000100) // Set Interrupt On Break
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constant SP_SINGLE_STEP_CLR($00000020)
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constant SP_SINGLE_STEP_SET($00000040)
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constant SP_INT_ON_BREAK_CLR($00000080) // Clear Interrupt On Break
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constant SP_INT_ON_BREAK_SET($00000100) // Set Interrupt On Break
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constant SP_SG0_CLR($00000200) // Clear Signal 0
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constant SP_SG0_SET($00000400) // Set Signal 0
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constant SP_SG1_CLR($00000800) // Clear Signal 1
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@ -60,33 +60,21 @@ constant SP_SG6_SET($00400000) // Set Signal 6
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constant SP_SG7_CLR($00800000) // Clear Signal 7
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constant SP_SG7_SET($01000000) // Set Signal 7
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macro SP_DMA_WAIT() { // from CPU
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lui t5, SP_BASE
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-
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lw t0, SP_DMA_FULL(t5)
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bnez t0,-
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nop
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-
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lw t0, SP_DMA_BUSY(t5)
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bnez t0,-
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nop
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}
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macro SP_BUSY_WAIT() {
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macro SP_DMA_WAIT() {
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lui a0, SP_BASE
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-
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lw t0, SP_STATUS(a0)
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andi t0, 0x1C
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andi t0, SP_IO_FULL | SP_BUSY | SP_FULL
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sltu t0, r0, t0
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bnez t0,-
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nop
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}
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macro SP_WAIT() {
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macro SP_HALT_WAIT() {
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lui a0, SP_BASE
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-
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lw t0, SP_STATUS(a0)
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andi t0, 1
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andi t0, SP_HALT
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beqz t0,-
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nop
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}
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37
main.asm
37
main.asm
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@ -24,11 +24,12 @@ include "kernel.asm"
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Main:
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lui s0, MAIN_BASE
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if 0 {
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nop; nop; nop; nop
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mfc0 t0, CP0_Count
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sw t0, MAIN_COUNTS+0(s0)
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if 0 {
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// decompress our picture
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la a0, LZ_BAKU + 4
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lw a3, -4(a0) // load uncompressed size from the file itself
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@ -36,7 +37,6 @@ if 0 {
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li a2, VIDEO_C_IMAGE
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jal LzDecomp
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nop
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}
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mfc0 t0, CP0_Count
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nop; nop; nop; nop
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@ -48,6 +48,7 @@ if 0 {
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jal PokeDataCache
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nop
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}
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lui a0, MAIN_BASE
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lli a1, 0x20
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@ -81,10 +82,10 @@ Start3D:
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// prepare RSP
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lui a0, SP_BASE
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lli t0, SP_SG2_CLR | SP_SG1_CLR | SP_SG0_CLR | SP_IOB_SET
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lli t0, SP_SG2_CLR | SP_SG1_CLR | SP_SG0_CLR | SP_INT_ON_BREAK_SET
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sw t0, SP_STATUS(a0)
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SP_WAIT()
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SP_HALT_WAIT()
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// set RSP PC to IMEM+$0
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lui a0, SP_PC_BASE
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@ -95,23 +96,25 @@ Start3D:
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jal PushVideoTask
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ori a0, a0, MAIN_SP_TASK
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SP_BUSY_WAIT()
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SP_DMA_WAIT()
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jal LoadRSPBoot
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nop
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SP_BUSY_WAIT()
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SP_DMA_WAIT()
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// clear all flags that would halt RSP (i.e. tell it to run!)
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lui a0, SP_BASE
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lli t0, SP_IOB_SET | SP_STP_CLR | SP_BRK_CLR | SP_HLT_CLR
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lli t0, SP_INT_ON_BREAK_SET | SP_SINGLE_STEP_CLR | SP_BREAK_CLR | SP_HALT_CLR
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sw t0, SP_STATUS(a0)
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nop
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SetIntMask()
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MainLoop:
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SP_WAIT()
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SP_HALT_WAIT()
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WriteString(SPreFrame)
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// wait on VI too
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-
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@ -139,6 +142,7 @@ SwitchToAlt:
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j Start3D
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lli s1, 1
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KSL(SPreFrame, "now waiting for VI")
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KSL(SNewFrame, "next frame")
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SetupScreen:
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@ -206,11 +210,12 @@ PushVideoTask:
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PushRSPTask:
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lli t3, 0x40 - 1 // DMA quirk
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SP_DMA_WAIT() // clobbers t0, t5
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or t4, a0, r0
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SP_DMA_WAIT() // clobbers t0, a0
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la t1, 0xA4000FC0
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sw t1, SP_MEM_ADDR(t5)
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sw a0, SP_DRAM_ADDR(t5)
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sw t3, SP_RD_LEN(t5) // pull data from RDRAM into DMEM/IMEM
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sw t1, SP_MEM_ADDR(a0)
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sw t4, SP_DRAM_ADDR(a0)
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sw t3, SP_RD_LEN(a0) // pull data from RDRAM into DMEM/IMEM
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jr ra
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nop
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@ -218,11 +223,11 @@ LoadRSPBoot:
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la t2, UCODE_BOOT & ADDR_MASK
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li t3, UCODE_BOOT.size
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subiu t3, t3, 1 // DMA quirk
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SP_DMA_WAIT() // clobbers t0, t5
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SP_DMA_WAIT() // clobbers t0, a0
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la t1, 0xA4001000
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sw t1, SP_MEM_ADDR(t5)
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sw t2, SP_DRAM_ADDR(t5)
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sw t3, SP_RD_LEN(t5) // pull data from RDRAM into DMEM/IMEM
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sw t1, SP_MEM_ADDR(a0)
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sw t2, SP_DRAM_ADDR(a0)
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sw t3, SP_RD_LEN(a0) // pull data from RDRAM into DMEM/IMEM
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jr ra
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nop
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