update includes with more/better constants
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5 changed files with 30 additions and 12 deletions
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@ -60,7 +60,7 @@ constant CP0_CAUSE_CE($30000000) // Coprocessor Error
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constant CP0_CAUSE_BD($80000000) // Branch Delay (not an exception, just info)
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// note that these constants are shifted left 2 into the Cause register,
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// so you must unshift the value from the register before comparing them.
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// so you must shift-right the value from the register before comparing them.
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constant CP0_CODE_INT(0) // Interrupt
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constant CP0_CODE_MOD(1) // TLB modification exception
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constant CP0_CODE_TLBL(2) // TLB Exception (Load or instruction fetch)
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@ -32,3 +32,5 @@ constant f29(29)
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constant f30(30)
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constant f31(31)
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constant CP1_Revision(0)
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constant CP1_FCSR(31)
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@ -12,11 +12,18 @@ constant MI_INTR_PI($10)
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constant MI_INTR_DP($20)
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constant MI_INTR_ALL($3F)
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// TODO: SET and CLR rather than just MASK
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constant MI_INTR_MASK_SP($002)
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constant MI_INTR_MASK_SI($008)
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constant MI_INTR_MASK_AI($020)
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constant MI_INTR_MASK_VI($080)
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constant MI_INTR_MASK_PI($200)
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constant MI_INTR_MASK_DP($800)
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constant MI_INTR_MASK_ALL($AAA)
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constant MI_INTR_MASK_SP_SET($002)
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constant MI_INTR_MASK_SI_SET($008)
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constant MI_INTR_MASK_AI_SET($020)
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constant MI_INTR_MASK_VI_SET($080)
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constant MI_INTR_MASK_PI_SET($200)
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constant MI_INTR_MASK_DP_SET($800)
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constant MI_INTR_MASK_ALL_SET($AAA)
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constant MI_INTR_MASK_SP_CLR($001)
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constant MI_INTR_MASK_SI_CLR($004)
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constant MI_INTR_MASK_AI_CLR($010)
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constant MI_INTR_MASK_VI_CLR($040)
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constant MI_INTR_MASK_PI_CLR($100)
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constant MI_INTR_MASK_DP_CLR($400)
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constant MI_INTR_MASK_ALL_CLR($555)
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@ -6,3 +6,13 @@ constant SI_PIF_ADDR_RD64B($04) // $04800004..$04800007 SI: Address Read 64B Reg
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constant SI_PIF_ADDR_WR64B($10) // $04800010..$04800013 SI: Address Write 64B Register
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//*RESERVED*($14) // $04800014..$04800017 SI: Reserved Register
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constant SI_STATUS($18) // $04800018..$0480001B SI: Status Register
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macro SI_WAIT() {
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lui a0, SI_BASE
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-
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lw t0, SI_STATUS(a0)
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andi t0, 0x0003
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sltu t0, r0, t0
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bnez t0,-
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nop
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}
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@ -34,9 +34,8 @@ Start:
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// enable even more interrupts.
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lui t2, MI_BASE
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ori t2, t2, MI_INTR_MASK
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lli t0, MI_INTR_MASK_ALL
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sw t0, 0(t2)
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lli t0, MI_INTR_MASK_ALL_SET
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sw t0, MI_INTR_MASK(t2)
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// set BSD DOM1 stuff, whatever that is.
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lui v1, CART_DOM1_ADDR2
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