diff --git a/inc/n64_cp0.inc b/inc/n64_cp0.inc
index 2a19f98..03a88d9 100644
--- a/inc/n64_cp0.inc
+++ b/inc/n64_cp0.inc
@@ -60,7 +60,7 @@ constant CP0_CAUSE_CE($30000000) // Coprocessor Error
 constant CP0_CAUSE_BD($80000000) // Branch Delay (not an exception, just info)
 
 // note that these constants are shifted left 2 into the Cause register,
-// so you must unshift the value from the register before comparing them.
+// so you must shift-right the value from the register before comparing them.
 constant CP0_CODE_INT(0)    // Interrupt
 constant CP0_CODE_MOD(1)    // TLB modification exception
 constant CP0_CODE_TLBL(2)   // TLB Exception (Load or instruction fetch)
diff --git a/inc/n64_cp1.inc b/inc/n64_cp1.inc
index 46d3142..12c37f9 100644
--- a/inc/n64_cp1.inc
+++ b/inc/n64_cp1.inc
@@ -32,3 +32,5 @@ constant f29(29)
 constant f30(30)
 constant f31(31)
 
+constant CP1_Revision(0)
+constant CP1_FCSR(31)
diff --git a/inc/n64_mi.inc b/inc/n64_mi.inc
index ed4acda..7affc73 100644
--- a/inc/n64_mi.inc
+++ b/inc/n64_mi.inc
@@ -12,11 +12,18 @@ constant MI_INTR_PI($10)
 constant MI_INTR_DP($20)
 constant MI_INTR_ALL($3F)
 
-// TODO: SET and CLR rather than just MASK
-constant MI_INTR_MASK_SP($002)
-constant MI_INTR_MASK_SI($008)
-constant MI_INTR_MASK_AI($020)
-constant MI_INTR_MASK_VI($080)
-constant MI_INTR_MASK_PI($200)
-constant MI_INTR_MASK_DP($800)
-constant MI_INTR_MASK_ALL($AAA)
+constant MI_INTR_MASK_SP_SET($002)
+constant MI_INTR_MASK_SI_SET($008)
+constant MI_INTR_MASK_AI_SET($020)
+constant MI_INTR_MASK_VI_SET($080)
+constant MI_INTR_MASK_PI_SET($200)
+constant MI_INTR_MASK_DP_SET($800)
+constant MI_INTR_MASK_ALL_SET($AAA)
+
+constant MI_INTR_MASK_SP_CLR($001)
+constant MI_INTR_MASK_SI_CLR($004)
+constant MI_INTR_MASK_AI_CLR($010)
+constant MI_INTR_MASK_VI_CLR($040)
+constant MI_INTR_MASK_PI_CLR($100)
+constant MI_INTR_MASK_DP_CLR($400)
+constant MI_INTR_MASK_ALL_CLR($555)
diff --git a/inc/n64_si.inc b/inc/n64_si.inc
index 5154a8f..8d54678 100644
--- a/inc/n64_si.inc
+++ b/inc/n64_si.inc
@@ -6,3 +6,13 @@ constant SI_PIF_ADDR_RD64B($04) // $04800004..$04800007 SI: Address Read 64B Reg
 constant SI_PIF_ADDR_WR64B($10) // $04800010..$04800013 SI: Address Write 64B Register
 //*RESERVED*($14)               // $04800014..$04800017 SI: Reserved Register
 constant SI_STATUS($18)         // $04800018..$0480001B SI: Status Register
+
+macro SI_WAIT() {
+    lui     a0, SI_BASE
+-
+    lw      t0, SI_STATUS(a0)
+    andi    t0, 0x0003
+    sltu    t0, r0, t0
+    bnez    t0,-
+    nop
+}
diff --git a/kernel.asm b/kernel.asm
index 038f071..ebeae42 100644
--- a/kernel.asm
+++ b/kernel.asm
@@ -34,9 +34,8 @@ Start:
 
     // enable even more interrupts.
     lui     t2, MI_BASE
-    ori     t2, t2, MI_INTR_MASK
-    lli     t0, MI_INTR_MASK_ALL
-    sw      t0, 0(t2)
+    lli     t0, MI_INTR_MASK_ALL_SET
+    sw      t0, MI_INTR_MASK(t2)
 
     // set BSD DOM1 stuff, whatever that is.
     lui     v1, CART_DOM1_ADDR2