2018-08-16 10:53:31 -07:00
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// built on the N64 ROM template by krom
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arch n64.cpu
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endian msb
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2018-08-18 08:31:58 -07:00
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include "inc/n64.inc"
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include "inc/n64_gfx.inc"
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include "inc/64drive.inc"
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2018-08-16 10:53:31 -07:00
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output "test.z64", create
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fill 1052672 // Set ROM Size
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origin 0x00000000
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base 0x80000000
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include "header.asm"
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2018-08-18 08:31:58 -07:00
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insert "bin/6102.bin"
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2018-08-16 10:53:31 -07:00
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// after inserting the header and bootrom,
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// origin should be at 0x1000.
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2018-08-18 08:31:58 -07:00
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include "inc/main.inc"
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2018-08-16 10:53:31 -07:00
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2018-08-18 10:44:23 -07:00
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include "inc/kernel.inc"
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2018-08-16 23:02:25 -07:00
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include "kernel.asm"
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2018-08-16 10:53:31 -07:00
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2018-08-16 23:02:25 -07:00
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nops(0x80010000)
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2018-08-16 10:53:31 -07:00
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2018-08-16 23:02:25 -07:00
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Main:
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lui t0, K_BASE
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2018-08-16 10:53:31 -07:00
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2018-08-16 23:02:25 -07:00
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lui s0, BLAH_BASE
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2018-08-18 15:22:24 -07:00
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mfc0 t1, CP0_Status+0
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sw t1, 8(s0)
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2018-08-16 10:53:31 -07:00
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2018-08-18 15:22:24 -07:00
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nop; nop; nop; nop
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2018-08-16 23:02:25 -07:00
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mfc0 t0, CP0_Count
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2018-08-16 10:53:31 -07:00
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sw t0, BLAH_COUNTS+0(s0)
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2018-08-18 15:22:24 -07:00
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// decompress our picture
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la a0, LZ_BAKU + 4
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lw a3, -4(a0) // load uncompressed size from the file itself
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li a1, LZ_BAKU.size - 4
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2018-08-19 17:13:11 -07:00
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li a2, VIDEO_C_BUFFER
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2018-08-18 15:22:24 -07:00
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jal LzDecomp
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nop
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2018-08-19 17:13:11 -07:00
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// TODO: flush cache on color buffer
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2018-08-16 10:53:31 -07:00
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2018-08-16 23:02:25 -07:00
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mfc0 t0, CP0_Count
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2018-08-18 15:22:24 -07:00
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nop; nop; nop; nop
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lw t1, BLAH_COUNTS+0(s0)
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2018-08-16 10:53:31 -07:00
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sw t0, BLAH_COUNTS+8(s0)
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2018-08-18 15:22:24 -07:00
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subu t1, t0, t1
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sw t1, BLAH_COUNTS+0xC(s0)
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2018-08-16 10:53:31 -07:00
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2018-08-19 17:13:11 -07:00
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// FIXME: this is triggering a PI interrupt somehow,
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// which is causing the IH debug output to be repeated instead!
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2018-08-16 10:53:31 -07:00
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lui a0, BLAH_BASE
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lli a1, 0x20
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ori a2, a0, BLAH_XXD
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2018-08-18 07:39:57 -07:00
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jal DumpAndWrite
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2018-08-16 10:53:31 -07:00
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lli a3, 0x20 * 4
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2018-08-18 07:39:57 -07:00
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InitVideo:
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2018-08-16 10:53:31 -07:00
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jal LoadRSPBoot
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nop
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lui a0, BLAH_BASE
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jal PushVideoTask
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ori a0, a0, BLAH_SP_TASK
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jal SetupScreen
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nop
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2018-08-16 23:02:25 -07:00
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mfc0 t0, CP0_Count
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2018-08-16 10:53:31 -07:00
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sw t0, BLAH_COUNTS+0xC(s0)
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2018-08-19 17:13:11 -07:00
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TestRDP:
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if 0 {
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// take a peek at the stuff at the Task data we wrote
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lui a0, BLAH_BASE
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ori a0, a0, BLAH_SP_TASK
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lli a1, 0x80
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ori a2, a0, BLAH_XXD
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jal DumpAndWrite
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lli a3, 0x80 * 4
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}
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// write the jump to our actual instructions
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lui a0, BLAH_BASE
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lui t0, 0xDE01 // jump (no push)
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sw t0, BLAH_DLIST_JUMPER+0(a0)
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ori t1, a0, BLAH_DLIST
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sw t1, BLAH_DLIST_JUMPER+4(a0)
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define dpos(BLAH_DLIST)
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macro WriteDL(evaluate L, evaluate R) {
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lui t0, ({L} >> 16) & 0xFFFF
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lui t1, ({R} >> 16) & 0xFFFF
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ori t0, {L} & 0xFFFF
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ori t1, {R} & 0xFFFF
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sw t0, {dpos}+0(a0)
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sw t1, {dpos}+4(a0)
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global evaluate dpos({dpos}+8)
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if {dpos} >= 0x8000 {
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error "much too much"
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// FIXME: just add dpos to a0 and set dpos to 0 when this happens
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}
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}
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// write some F3DZEX instructions
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{
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// G_RDPPIPESYNC
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WriteDL(0xE7000000, 0)
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// G_TEXTURE (disable tile descriptor; dummy second argument)
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WriteDL(0xD7000000, 0xFFFFFFFF)
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// G_SETCOMBINE (too complicated to explain here...)
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WriteDL(0xFCFFFFFF, 0xFFFE793C)
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// G_RDPSETOTHERMODE (set higher flags, clear all lower flags)
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// 0011 1000 0010 1100 0011 0000
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// G_AD_DISABLE | G_CD_MAGICSQ | G_TC_FILT | G_TF_BILERP |
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// G_TT_NONE | G_TL_TILE | G_TD_CLAMP | G_MDSFT_TEXTPERSP |
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// G_CYC_FILL | G_PM_NPRIMITIVE
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WriteDL(0xEF382C30, 0x00000000)
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// G_GEOMETRYMODE
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// set some bits (TODO: which?), clear none
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WriteDL(0xD9000000, 0x00220405)
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// G_SETSCISSOR coordinate order: (top, left), (right, bottom)
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WriteDL(0xED000000 | (0 << 14) | (0 << 2), (320 << 14) | (240 << 2))
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// G_SETBLENDCOLOR
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// sets alpha component to 8, everything else to 0
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WriteDL(0xF9000000, 0x00000008)
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// sets near-far plane clipping? maybe?
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// G_MOVEWORD, sets G_MW_CLIP+$0004
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WriteDL(0xDB040004, 2)
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// G_MOVEWORD, sets G_MW_CLIP+$000C
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WriteDL(0xDB04000C, 2)
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// G_MOVEWORD, sets G_MW_CLIP+$0014
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WriteDL(0xDB040014, 0x10000 - 2)
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// G_MOVEWORD, sets G_MW_CLIP+$001C
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WriteDL(0xDB04001C, 0x10000 - 2)
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// G_ENDDL: absent since we're not jumping to this routine
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}
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// G_SETCIMG, set our color buffer (fmt 0, bit size %10, width)
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WriteDL(0xFF100000 | (640 - 1), VIDEO_C_BUFFER)
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// G_SETZIMG, set our z buffer (fmt 0, bit size %00, width)
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WriteDL(0xFE000000, VIDEO_Z_BUFFER)
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// G_SETFILLCOLOR
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WriteDL(0xF7000000, 0xFFFFFFFF)
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// G_FILLRECT coordinate order: (right, bottom), (top, left)
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// note that the coordinates are all inclusive!
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WriteDL(0xF6000000 | (199 << 14) | (199 << 2), (100 << 14) | (100 << 2))
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// G_RDPPIPESYNC
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WriteDL(0xE7000000, 0)
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// always finish it off by telling RDP to stop!
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// G_RDPFULLSYNC, G_ENDDL
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WriteDL(0xE9000000, 0); WriteDL(0xDF000000, 0)
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// take a peek at the display list we wrote
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lui a0, BLAH_BASE
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ori a0, BLAH_DLIST
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lli a1, 0x80
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ori a2, a0, BLAH_XXD
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jal DumpAndWrite
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lli a3, 0x80 * 4
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// stuff i'm borrowing from zelda:
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lui a0, SP_BASE
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lli t0, CLR_SG2 | CLR_SG1 | CLR_SG0 | SET_IOB
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sw t0, SP_STATUS(a0)
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// NOTE: we should be asserting here that SP_STATUS & 1 != 0
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// set RSP PC to IMEM+$0
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lui a0, SP_PC_BASE
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li t0, 0x04001000
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sw t0, SP_PC(a0)
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// tell RSP to run by clearing flags
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lui a0, SP_BASE
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lli t0, SET_IOB | CLR_STP | CLR_BRK | CLR_HLT
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sw t0, SP_STATUS(a0)
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nop
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// also one thing i noticed in zelda is they set VI_V_INTR to 2
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// so they get interrupts with scanlines (unlike us who just waits)
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2018-08-16 10:53:31 -07:00
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MainLoop:
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// borrowing code from krom for now:
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WaitScanline(0x1E0) // Wait For Scanline To Reach Vertical Blank
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WaitScanline(0x1E2)
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// WaitScanline sets a0
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2018-08-19 17:13:11 -07:00
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li t0, 0x00000800 // Even Field
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2018-08-16 10:53:31 -07:00
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sw t0, VI_Y_SCALE(a0)
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WaitScanline(0x1E0) // Wait For Scanline To Reach Vertical Blank
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WaitScanline(0x1E2)
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// WaitScanline sets a0
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li t0, 0x02000800 // Odd Field
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sw t0, VI_Y_SCALE(a0)
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j MainLoop
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nop // delay slot
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SetupScreen:
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2018-08-19 17:13:11 -07:00
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// NTSC: 640x480, 32BPP, Interlace, Resample Only, DRAM Origin VIDEO_C_BUFFER
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ScreenNTSC(640, 480, BPP32|INTERLACE|AA_MODE_2, VIDEO_C_BUFFER | UNCACHED)
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2018-08-16 10:53:31 -07:00
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jr ra
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nop
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LoadRSPBoot:
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li t2, F3DZEX_BOOT
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li t3, F3DZEX_BOOT.size
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subiu t3, t3, 1 // DMA quirk
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SP_DMA_WAIT() // clobbers t0, t5
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2018-08-19 17:13:11 -07:00
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// ori t1, t5, 0x1000
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la t1, 0xA4001000
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2018-08-16 10:53:31 -07:00
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sw t1, SP_MEM_ADDR(t5)
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sw t2, SP_DRAM_ADDR(t5)
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sw t3, SP_RD_LEN(t5) // pull data from RDRAM into DMEM/IMEM
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jr ra
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nop
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PushVideoTask:
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2018-08-19 17:13:11 -07:00
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// a0: Task RDRAM Pointer (size: 0x40) (should probably be row-aligned)
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2018-08-16 23:53:37 -07:00
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subiu sp, sp, 0x18
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sw ra, 0x10(sp)
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2018-08-16 10:53:31 -07:00
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lli t0, 1 // mode: video
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lli t1, 4 // flags: ???
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2018-08-19 17:13:11 -07:00
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li t2, F3DZEX_BOOT // does not need masking for some reason
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2018-08-16 10:53:31 -07:00
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li t3, F3DZEX_BOOT.size
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li t4, F3DZEX_IMEM & ADDR_MASK
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li t5, F3DZEX_IMEM.size // note: Zelda uses 0x1000 for some reason (0x80 too big).
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li t6, F3DZEX_DMEM & ADDR_MASK
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li t7, F3DZEX_DMEM.size // note: Zelda uses 0x800 for some reason (way too big).
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sw t0, 0x00(a0)
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sw t1, 0x04(a0)
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sw t2, 0x08(a0)
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sw t3, 0x0C(a0)
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sw t4, 0x10(a0)
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sw t5, 0x14(a0)
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sw t6, 0x18(a0)
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sw t7, 0x1C(a0)
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2018-08-16 23:02:25 -07:00
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li t0, VIDEO_STACK & ADDR_MASK // used for DList calls and returns?
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2018-08-16 10:53:31 -07:00
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li t1, VIDEO_STACK_SIZE
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2018-08-19 17:13:11 -07:00
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li t2, VIDEO_SOMETHING & ADDR_MASK
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li t3, (VIDEO_SOMETHING & ADDR_MASK) + VIDEO_SOMETHING_SIZE // end pointer (not size!)
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2018-08-16 14:02:08 -07:00
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li t4, ((BLAH_BASE << 16) | BLAH_DLIST_JUMPER) & ADDR_MASK // initial DList
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2018-08-16 10:53:31 -07:00
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lli t5, 8 // size of one jump command
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li t6, VIDEO_YIELD & ADDR_MASK
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li t7, VIDEO_YIELD_SIZE
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sw t0, 0x20(a0)
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sw t1, 0x24(a0)
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sw t2, 0x28(a0)
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sw t3, 0x2C(a0)
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sw t4, 0x30(a0)
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sw t5, 0x34(a0)
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sw t6, 0x38(a0)
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sw t7, 0x3C(a0)
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2018-08-19 17:13:11 -07:00
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// tell data cache to write itself out
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cache 0x19, 0x00(a0)
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cache 0x19, 0x10(a0)
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cache 0x19, 0x20(a0)
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cache 0x19, 0x30(a0)
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li t9, ADDR_MASK
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jal PushRSPTask
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and a0, a0, t9
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2018-08-16 10:53:31 -07:00
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2018-08-16 23:53:37 -07:00
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lw ra, 0x10(sp)
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2018-08-16 10:53:31 -07:00
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jr ra
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2018-08-16 23:53:37 -07:00
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addiu sp, sp, 0x18
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2018-08-16 10:53:31 -07:00
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PushRSPTask:
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lli t3, 0x40 - 1 // DMA quirk
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SP_DMA_WAIT() // clobbers t0, t5
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2018-08-19 17:13:11 -07:00
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// ori t1, t5, 0xFC0
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la t1, 0xA4000FC0
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2018-08-16 10:53:31 -07:00
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sw t1, SP_MEM_ADDR(t5)
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sw a0, SP_DRAM_ADDR(t5)
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sw t3, SP_RD_LEN(t5) // pull data from RDRAM into DMEM/IMEM
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jr ra
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nop
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2018-08-18 15:22:24 -07:00
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include "lzss.baku.unsafe.asm"
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2018-08-18 08:31:58 -07:00
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align(16); insert F3DZEX_BOOT, "bin/F3DZEX2.boot.bin"
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align(16); insert F3DZEX_DMEM, "bin/F3DZEX2.data.bin"
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align(16); insert F3DZEX_IMEM, "bin/F3DZEX2.bin"
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align(16); insert FONT, "res/dwarf.1bpp"
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2018-08-18 15:22:24 -07:00
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align(16); insert LZ_BAKU, "res/Image.baku.lzss"
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