init
This commit is contained in:
commit
5f143cae81
10
.gitignore
vendored
Normal file
10
.gitignore
vendored
Normal file
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@ -0,0 +1,10 @@
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|||
old.asm
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_old
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microcodes
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||||
*.bin
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||||
!F3DZEX2.data.bin
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||||
!6102.bin
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||||
*.z64
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||||
*.c
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||||
*.tmp
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||||
*.txt
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||||
34
64drive.inc
Normal file
34
64drive.inc
Normal file
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@ -0,0 +1,34 @@
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|||
// set 64Drive interface constants.
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||||
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||||
// NOTE: although STATUSes are marked as halfwords,
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// you should use lw/sw to interact with them.
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||||
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||||
constant CI_BASE($B800)
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constant CI_BASE_EXTENDED($BF80)
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constant CI_GENERAL_BUFFER($0000) // 512 bytes
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constant CI_STATUS($0200) // halfword
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constant CI_COMMAND($0208) // word
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constant CI_LBA($0210) // word
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constant CI_LENGTH($0218) // word
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constant CI_RESULT($0220) // word
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constant CI_SDRAM_SIZE($02E8) // word
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constant CI_HW_MAGIC($02EC) // word ("UDEV")
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constant CI_HW_VARIANT($02F0) // word
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constant CI_PERSISTENT($02F4) // word (RESERVED)
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constant CI_BUTTON_STATUS($02F8) // halfword (needs debouncing)
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constant CI_UPGRADE_MOD_STATUS($02FA) // halfword
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constant CI_REVISION_NUMBER($02FC) // halfword
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constant CI_USB_COMMAND_STATUS($0400) // byte
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constant CI_USB_PARAM_RESULT_0($0404) // word
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constant CI_USB_PARAM_RESULT_1($0408) // word
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constant CI_WIFI_COMMAND_STATUS($0420) // byte
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constant CI_WIFI_PARAM_RESULT_0($0424) // word
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constant CI_WIFI_PARAM_RESULT_1($0428) // word
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constant CI_EEPROM($1000) // 2048 bytes
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constant CI_WRITEBACK_LBA($1800) // 1024 bytes (256 words)
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1049
F3DZEX.asm
Normal file
1049
F3DZEX.asm
Normal file
File diff suppressed because it is too large
Load Diff
BIN
F3DZEX2.data.bin
Normal file
BIN
F3DZEX2.data.bin
Normal file
Binary file not shown.
3
README.md
Normal file
3
README.md
Normal file
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@ -0,0 +1,3 @@
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nothing to see here (yet).
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currently borrowing some code from [krom's repo.](https://github.com/PeterLemon/N64/)
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14
build
Normal file
14
build
Normal file
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@ -0,0 +1,14 @@
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#!/usr/bin/env bash
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# TODO: make this crap actually portable
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set -e
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ROM_NAME=test.z64
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#while inotifywait -q -e create,modify *.asm *.inc; do
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bass F3DZEX.asm
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bass main.asm
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/tmp/z64crc "$ROM_NAME"
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#done
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# don't use -z in msys2 because it hangs
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64drive_usb -c 1 -l "$ROM_NAME" #-z
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78
devcart.asm
Normal file
78
devcart.asm
Normal file
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@ -0,0 +1,78 @@
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// debug routines for the 64drive, not a real devcart!
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Drive64Write:
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// a0: RAM address to copy from
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// a1: length of data to copy in bytes
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// v0: error code (0 is OK)
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// TODO: a0 should be double-word aligned if used directly with DMA
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// assert a0 (RAM address) is word-aligned
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andi t9, a0, 3
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bnezl t9, Drive64WriteExit
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lli v0, 1
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// assert a1 (copy length) is word-aligned
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andi t9, a1, 3
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bnezl t9, Drive64WriteExit
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lli v0, 2
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blez a1, Drive64WriteExit // nothing to write? nothing to do!
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lli v0, 0 // delay slot
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lui a2, 0x103F // SDRAM destination
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move a3, a1 // SDRAM length
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// flush the cache at a0 to RAM before doing any DMA
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andi t6, a0, 0xF
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addu t7, a0, a1 // stop flushing around here
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subu t6, a0, t6 // align a0 to data line
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subiu t7, t7, 1 // turn inclusive end-point into exclusive instead
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-
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cache 1, 0(t6) // peter says: "Index Writeback Invalidate"
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sltu at, t6, t7
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bnez at,-
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addiu t6, 0x10 // (delay slot) += data line size
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// AND off the DRAM address
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li t9, 0x007FFFFF // __osPiRawStartDma uses 0x1FFFFFFF?
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and t1, a0, t9
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// cart address
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move t2, a2
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// set length (needs to be decremented due to DMA quirk)
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subiu t3, a3, 1
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PI_WAIT()
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sw t1, PI_DRAM_ADDR(t5)
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sw t2, PI_CART_ADDR(t5)
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sw t3, PI_RD_LEN(t5) // "read" from DRAM to cart
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// PI_WAIT() // if we always wait before doing operations, this shouldn't be necessary
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Drive64TestPoint:
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lui at, 0x0100 // set printf channel
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or a3, a3, at
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lli t1, 0x08 // WRITE mode
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// SDRAM parameter is given in multiples of halfwords
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li t9, 0x0FFFFFFF
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and a2, a2, t9
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srl a2, a2, 1
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CI_USB_WRITE_WAIT()
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sw a2, CI_USB_PARAM_RESULT_0(gp)
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PI_WAIT() // yes, these waits seem to be necessary
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sw a3, CI_USB_PARAM_RESULT_1(gp)
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PI_WAIT()
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sw t1, CI_USB_COMMAND_STATUS(gp)
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// CI_USB_WRITE_WAIT() // if we always wait before doing operations, this shouldn't be necessary
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Drive64WriteExit:
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jr ra
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nop // delay slot
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Drive64TestWrite:
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li a2, 0xA0000020
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lli a3, 0x20
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j Drive64TestPoint
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nop // delay slot
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BIN
dwarf.1bpp
Normal file
BIN
dwarf.1bpp
Normal file
Binary file not shown.
38
header.asm
Normal file
38
header.asm
Normal file
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@ -0,0 +1,38 @@
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//============
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// N64 Header
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//============
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// PI_BSB_DOM1
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db $80 // Initial PI_BSB_DOM1_LAT_REG Value
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db $37 // Initial PI_BSB_DOM1_PGS_REG Value
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db $12 // Initial PI_BSB_DOM1_PWD_REG Value
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db $40 // Initial PI_BSB_DOM1_PGS_REG Value
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// CLOCK RATE
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dw $000F // Initial Clock Rate
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||||
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||||
// VECTOR
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dw Start // Boot Address Offset
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||||
dw $1444 // Release Offset
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||||
// COMPLEMENT CHECK & CHECKSUM
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db "CRC1" // CRC1: COMPLEMENT CHECK
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db "CRC2" // CRC2: CHECKSUM
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dd 0 // UNUSED
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// PROGRAM TITLE (27 Byte ASCII String, Use Spaces For Unused Bytes)
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db "NOTWA'S TESTING THE 64DRIVE"
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// "123456789012345678901234567"
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// DEVELOPER ID CODE
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db $00 // "N" = Nintendo
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// CARTRIDGE ID CODE
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db $00
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db 0 // UNUSED
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||||
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// COUNTRY CODE
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db $00 // "D" = Germany, "E" = USA, "J" = Japan, "P" = Europe, "U" = Australia
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db 0 // UNUSED
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55
lz.asm
Normal file
55
lz.asm
Normal file
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@ -0,0 +1,55 @@
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|||
// by krom (Peter Lemon)
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// https://github.com/PeterLemon/N64/tree/master/Compress/LZ77/LZ77GFX
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LZInit:
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la a0, LZ+4 // A0 = Source Address
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lui a1, 0xA010 // A1 = Destination Address (DRAM Start Offset)
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lbu t0, -1(a0) // T0 = HI Data Length Byte
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sll t0, 8
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lbu t1, -2(a0) // T1 = MID Data Length Byte
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or t0, t1
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sll t0, 8
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lbu t1, -3(a0) // T1 = LO Data Length Byte
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or t0, t1 // T0 = Data Length
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addu t0, a1 // T0 = Destination End Offset (DRAM End Offset)
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LZLoop:
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lbu t1, 0(a0) // T1 = Flag Data For Next 8 Blocks (0 = Uncompressed Byte, 1 = Compressed Bytes)
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addiu a0, 1 // Add 1 To LZ Offset
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ori t2, r0, %10000000 // T2 = Flag Data Block Type Shifter
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LZBlockLoop:
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beq a1, t0, LZEnd // IF (Destination Address == Destination End Offset) LZEnd
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and t4, t1, t2 // Test Block Type (Delay Slot)
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beqz t2, LZLoop // IF (Flag Data Block Type Shifter == 0) LZLoop
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srl t2, 1 // Shift T2 To Next Flag Data Block Type (Delay Slot)
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lbu t3, 0(a0) // T3 = Copy Uncompressed Byte / Number Of Bytes To Copy & Disp MSB's
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bnez t4, LZDecode // IF (BlockType != 0) LZDecode Bytes
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addiu a0, 1 // Add 1 To LZ Offset (Delay Slot)
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sb t3, 0(a1) // Store Uncompressed Byte To Destination
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j LZBlockLoop
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addiu a1, 1 // Add 1 To DRAM Offset (Delay Slot)
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||||
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LZDecode:
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lbu t4, 0(a0) // T4 = Disp LSB's
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addiu a0, 1 // Add 1 To LZ Offset
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||||
sll t5, t3, 8 // T5 = Disp MSB's
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or t4, t5 // T4 = Disp 16-Bit
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andi t4, 0xFFF // T4 &= 0xFFF (Disp 12-Bit)
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not t4 // T4 = -Disp - 1
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addu t4, a1 // T4 = Destination - Disp - 1
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srl t3, 4 // T3 = Number Of Bytes To Copy (Minus 3)
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addiu t3, 3 // T3 = Number Of Bytes To Copy
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LZCopy:
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lbu t5, 0(t4) // T5 = Byte To Copy
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addiu t4, 1 // Add 1 To T4 Offset
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sb t5, 0(a1) // Store Byte To DRAM
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subiu t3, 1 // Number Of Bytes To Copy -= 1
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bnez t3, LZCopy // IF (Number Of Bytes To Copy != 0) LZCopy Bytes
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||||
addiu a1, 1 // Add 1 To DRAM Offset (Delay Slot)
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j LZBlockLoop
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nop // Delay Slot
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||||
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||||
LZEnd:
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||||
217
main.asm
Normal file
217
main.asm
Normal file
|
|
@ -0,0 +1,217 @@
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|||
// built on the N64 ROM template by krom
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arch n64.cpu
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||||
endian msb
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||||
include "n64.inc"
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include "n64_gfx.inc"
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||||
include "64drive.inc"
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|
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output "test.z64", create
|
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fill 1052672 // Set ROM Size
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||||
|
||||
origin 0x00000000
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base 0x80000000
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||||
|
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include "header.asm"
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||||
insert "6102.bin"
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||||
// after inserting the header and bootrom,
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||||
// origin should be at 0x1000.
|
||||
|
||||
include "main.inc"
|
||||
|
||||
Start:
|
||||
N64_INIT() // enable interrupts
|
||||
|
||||
// SP defaults to RSP instruction memory: 0xA4001FF0
|
||||
// we can do better than that.
|
||||
lui sp, BLAH_BASE
|
||||
// SP should always be 8-byte aligned
|
||||
// so that SD and LD instructions don't fail on it.
|
||||
subiu sp, sp, 8
|
||||
|
||||
lui s0, BLAH_BASE
|
||||
|
||||
Drive64Init:
|
||||
lui gp, CI_BASE
|
||||
lui t2, 0x5544 // "UD" of "UDEV"
|
||||
lw t1, CI_HW_MAGIC(gp)
|
||||
ori t2, t2, 0x4556 // "EV" of "UDEV"
|
||||
|
||||
beq t1, t2, Drive64Confirmed
|
||||
nop // delay slot
|
||||
|
||||
Drive64TryExtended:
|
||||
lui gp, CI_BASE_EXTENDED
|
||||
lw t1, CI_HW_MAGIC(gp)
|
||||
bne t1, t2, Main
|
||||
nop // delay slot
|
||||
|
||||
Drive64Confirmed:
|
||||
sw t2, BLAH_CONFIRMED(s0)
|
||||
sw gp, BLAH_CI_BASE(s0)
|
||||
|
||||
// enable writing to cartROM (SDRAM) for USB writing later
|
||||
lli t1, 0xF0
|
||||
|
||||
CI_WAIT()
|
||||
sw t1, CI_COMMAND(gp) // send our command
|
||||
CI_WAIT()
|
||||
|
||||
Main:
|
||||
if 0 {
|
||||
mfc0 t0, 0x9 // move cycle Count register from COP 0
|
||||
sw t0, BLAH_COUNTS+0(s0)
|
||||
mfc0 t0, 0x9 // move cycle Count register from COP 0
|
||||
sw t0, BLAH_COUNTS+4(s0)
|
||||
// seems like 41 half-cycles between the two mfc0's, rarely 42?
|
||||
} else {
|
||||
mfc0 t0, 0x9
|
||||
mfc0 t1, 0x9
|
||||
sw t0, BLAH_COUNTS+0(s0)
|
||||
sw t1, BLAH_COUNTS+4(s0)
|
||||
// seems like 22 half-cycles between the two mfc0's
|
||||
}
|
||||
|
||||
// what is our stack pointer set to, anyway?
|
||||
sw sp, 0xC(s0)
|
||||
|
||||
// decompress our picture
|
||||
include "lz.asm"
|
||||
|
||||
mfc0 t0, 0x9
|
||||
sw t0, BLAH_COUNTS+8(s0)
|
||||
lw t1, BLAH_CONFIRMED(s0)
|
||||
beqz t1, InitVideo
|
||||
nop // delay slot
|
||||
|
||||
// jal Drive64TestWrite
|
||||
// nop // delay slot
|
||||
|
||||
lui a0, BLAH_BASE
|
||||
lli a1, 0x20
|
||||
ori a2, a0, BLAH_XXD
|
||||
lli a3, 0x20 * 4
|
||||
jal xxd
|
||||
nop // delay slot
|
||||
|
||||
lui a0, BLAH_BASE // write address
|
||||
ori a0, a0, BLAH_XXD // (RAM gets copied to SDRAM by routine)
|
||||
lli a1, 0x20 * 4
|
||||
jal Drive64Write
|
||||
nop // delay slot
|
||||
|
||||
InitVideo: // currently 80001190 (this comment is likely out of date)
|
||||
// A4000FC0
|
||||
|
||||
jal LoadRSPBoot
|
||||
nop
|
||||
|
||||
lui a0, BLAH_BASE
|
||||
jal PushVideoTask
|
||||
ori a0, a0, BLAH_SP_TASK
|
||||
|
||||
jal SetupScreen
|
||||
nop
|
||||
|
||||
mfc0 t0, 0x9 // move cycle Count register from COP 0
|
||||
sw t0, BLAH_COUNTS+0xC(s0)
|
||||
|
||||
MainLoop:
|
||||
// borrowing code from krom for now:
|
||||
WaitScanline(0x1E0) // Wait For Scanline To Reach Vertical Blank
|
||||
WaitScanline(0x1E2)
|
||||
// WaitScanline sets a0
|
||||
|
||||
ori t0, r0, 0x00000800 // Even Field
|
||||
sw t0, VI_Y_SCALE(a0)
|
||||
|
||||
WaitScanline(0x1E0) // Wait For Scanline To Reach Vertical Blank
|
||||
WaitScanline(0x1E2)
|
||||
// WaitScanline sets a0
|
||||
|
||||
li t0, 0x02000800 // Odd Field
|
||||
sw t0, VI_Y_SCALE(a0)
|
||||
|
||||
j MainLoop
|
||||
nop // delay slot
|
||||
|
||||
include "devcart.asm" // assumes gp is set to CI base
|
||||
|
||||
SetupScreen:
|
||||
// NTSC: 640x480, 32BPP, Interlace, Resample Only, DRAM Origin VIDEO_BUFFER
|
||||
ScreenNTSC(640, 480, BPP32|INTERLACE|AA_MODE_2, VIDEO_BUFFER | UNCACHED)
|
||||
jr ra
|
||||
nop
|
||||
|
||||
LoadRSPBoot:
|
||||
li t2, F3DZEX_BOOT
|
||||
li t3, F3DZEX_BOOT.size
|
||||
subiu t3, t3, 1 // DMA quirk
|
||||
SP_DMA_WAIT() // clobbers t0, t5
|
||||
ori t1, t5, 0x1000
|
||||
sw t1, SP_MEM_ADDR(t5)
|
||||
sw t2, SP_DRAM_ADDR(t5)
|
||||
sw t3, SP_RD_LEN(t5) // pull data from RDRAM into DMEM/IMEM
|
||||
jr ra
|
||||
nop
|
||||
|
||||
PushVideoTask:
|
||||
// a0: Task RDRAM Pointer (size: 0x40)
|
||||
subiu sp, sp, 0x8
|
||||
sw ra, 0(sp)
|
||||
|
||||
lli t0, 1 // mode: video
|
||||
lli t1, 4 // flags: ???
|
||||
li t2, F3DZEX_BOOT
|
||||
li t3, F3DZEX_BOOT.size
|
||||
li t4, F3DZEX_IMEM & ADDR_MASK
|
||||
li t5, F3DZEX_IMEM.size // note: Zelda uses 0x1000 for some reason (0x80 too big).
|
||||
li t6, F3DZEX_DMEM & ADDR_MASK
|
||||
li t7, F3DZEX_DMEM.size // note: Zelda uses 0x800 for some reason (way too big).
|
||||
sw t0, 0x00(a0)
|
||||
sw t1, 0x04(a0)
|
||||
sw t2, 0x08(a0)
|
||||
sw t3, 0x0C(a0)
|
||||
sw t4, 0x10(a0)
|
||||
sw t5, 0x14(a0)
|
||||
sw t6, 0x18(a0)
|
||||
sw t7, 0x1C(a0)
|
||||
li t0, VIDEO_STACK & ADDR_MASK // ?
|
||||
li t1, VIDEO_STACK_SIZE
|
||||
li t2, VIDEO_BUFFER & ADDR_MASK
|
||||
li t3, (VIDEO_BUFFER & ADDR_MASK) + VIDEO_BUFFER_SIZE // end pointer (not size!)
|
||||
li t4, BLAH_DLIST_JUMPER & ADDR_MASK // initial DList (best to just be one jump command)
|
||||
lli t5, 8 // size of one jump command
|
||||
li t6, VIDEO_YIELD & ADDR_MASK
|
||||
li t7, VIDEO_YIELD_SIZE
|
||||
sw t0, 0x20(a0)
|
||||
sw t1, 0x24(a0)
|
||||
sw t2, 0x28(a0)
|
||||
sw t3, 0x2C(a0)
|
||||
sw t4, 0x30(a0)
|
||||
sw t5, 0x34(a0)
|
||||
sw t6, 0x38(a0)
|
||||
sw t7, 0x3C(a0)
|
||||
jal PushRSPTask // a0 passthru
|
||||
nop
|
||||
|
||||
lw ra, 0(sp)
|
||||
jr ra
|
||||
addiu sp, sp, 0x8
|
||||
|
||||
PushRSPTask:
|
||||
lli t3, 0x40 - 1 // DMA quirk
|
||||
SP_DMA_WAIT() // clobbers t0, t5
|
||||
ori t1, t5, 0xFC0
|
||||
sw t1, SP_MEM_ADDR(t5)
|
||||
sw a0, SP_DRAM_ADDR(t5)
|
||||
sw t3, SP_RD_LEN(t5) // pull data from RDRAM into DMEM/IMEM
|
||||
jr ra
|
||||
nop
|
||||
|
||||
include "xxd.asm"
|
||||
|
||||
align(16); insert F3DZEX_BOOT, "F3DZEX2.boot.bin"
|
||||
align(16); insert F3DZEX_DMEM, "F3DZEX2.data.bin"
|
||||
align(16); insert F3DZEX_IMEM, "F3DZEX2.bin"
|
||||
align(16); insert FONT, "dwarf.1bpp"
|
||||
align(16); insert LZ, "Image.lz"
|
||||
56
main.inc
Normal file
56
main.inc
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
constant UNCACHED(0xA0000000)
|
||||
constant ADDR_MASK(0x1FFFFFFF)
|
||||
|
||||
constant BLAH_BASE(0x803F)
|
||||
constant BLAH_CONFIRMED(0x0000)
|
||||
constant BLAH_CI_BASE(0x0004)
|
||||
constant BLAH_COUNTS(0x0010)
|
||||
constant BLAH_SP_TASK(0x0040)
|
||||
constant BLAH_DLIST_JUMPER(0x0080)
|
||||
constant BLAH_XXD(0x0100)
|
||||
constant VIDEO_BUFFER(0x80100000)
|
||||
constant VIDEO_BUFFER_SIZE(640 * 480 * 4)
|
||||
constant VIDEO_STACK(VIDEO_BUFFER + VIDEO_BUFFER_SIZE)
|
||||
constant VIDEO_STACK_SIZE(0x400)
|
||||
constant VIDEO_YIELD(VIDEO_STACK + VIDEO_STACK_SIZE)
|
||||
constant VIDEO_YIELD_SIZE(0xC00)
|
||||
|
||||
macro PI_WAIT() {
|
||||
lui t5, PI_BASE
|
||||
-
|
||||
lw t0, PI_STATUS(t5)
|
||||
andi t0, t0, 3
|
||||
bnez t0,-
|
||||
nop // delay slot
|
||||
}
|
||||
|
||||
macro SP_DMA_WAIT() { // external
|
||||
lui t5, SP_BASE
|
||||
-
|
||||
lw t0, SP_DMA_FULL(t5)
|
||||
bnez t0,-
|
||||
nop
|
||||
-
|
||||
lw t0, SP_DMA_BUSY(t5)
|
||||
bnez t0,-
|
||||
nop
|
||||
}
|
||||
|
||||
macro CI_WAIT() {
|
||||
PI_WAIT()
|
||||
-
|
||||
lw t0, CI_STATUS(gp)
|
||||
srl t0, t0, 12 // first 12 bits are reserved, so ignore them
|
||||
bnez t0,-
|
||||
nop // delay slot
|
||||
}
|
||||
|
||||
macro CI_USB_WRITE_WAIT() {
|
||||
PI_WAIT()
|
||||
-
|
||||
lw t0, CI_USB_COMMAND_STATUS(gp)
|
||||
srl t0, t0, 4 // shift out ARM status, leaving WRITE status
|
||||
bnez t0,-
|
||||
nop // delay slot
|
||||
}
|
||||
|
||||
267
n64.inc
Normal file
267
n64.inc
Normal file
|
|
@ -0,0 +1,267 @@
|
|||
// via krom
|
||||
|
||||
//=============
|
||||
// N64 Include
|
||||
//=============
|
||||
// N64 MIPS 4300 CPU Registers
|
||||
constant r0(0)
|
||||
constant r1(1)
|
||||
constant r2(2)
|
||||
constant r3(3)
|
||||
constant r4(4)
|
||||
constant r5(5)
|
||||
constant r6(6)
|
||||
constant r7(7)
|
||||
constant r8(8)
|
||||
constant r9(9)
|
||||
constant r10(10)
|
||||
constant r11(11)
|
||||
constant r12(12)
|
||||
constant r13(13)
|
||||
constant r14(14)
|
||||
constant r15(15)
|
||||
constant r16(16)
|
||||
constant r17(17)
|
||||
constant r18(18)
|
||||
constant r19(19)
|
||||
constant r20(20)
|
||||
constant r21(21)
|
||||
constant r22(22)
|
||||
constant r23(23)
|
||||
constant r24(24)
|
||||
constant r25(25)
|
||||
constant r26(26)
|
||||
constant r27(27)
|
||||
constant r28(28)
|
||||
constant r29(29)
|
||||
constant r30(30)
|
||||
constant r31(31)
|
||||
|
||||
constant at(1)
|
||||
constant v0(2)
|
||||
constant v1(3)
|
||||
constant a0(4)
|
||||
constant a1(5)
|
||||
constant a2(6)
|
||||
constant a3(7)
|
||||
constant t0(8)
|
||||
constant t1(9)
|
||||
constant t2(10)
|
||||
constant t3(11)
|
||||
constant t4(12)
|
||||
constant t5(13)
|
||||
constant t6(14)
|
||||
constant t7(15)
|
||||
constant s0(16)
|
||||
constant s1(17)
|
||||
constant s2(18)
|
||||
constant s3(19)
|
||||
constant s4(20)
|
||||
constant s5(21)
|
||||
constant s6(22)
|
||||
constant s7(23)
|
||||
constant t8(24)
|
||||
constant t9(25)
|
||||
constant k0(26)
|
||||
constant k1(27)
|
||||
constant gp(28)
|
||||
constant sp(29)
|
||||
constant s8(30)
|
||||
constant ra(31)
|
||||
|
||||
// N64 MIPS 4300 CP1 Floating Point Unit (FPU) Registers (COP1)
|
||||
constant f0(0)
|
||||
constant f1(1)
|
||||
constant f2(2)
|
||||
constant f3(3)
|
||||
constant f4(4)
|
||||
constant f5(5)
|
||||
constant f6(6)
|
||||
constant f7(7)
|
||||
constant f8(8)
|
||||
constant f9(9)
|
||||
constant f10(10)
|
||||
constant f11(11)
|
||||
constant f12(12)
|
||||
constant f13(13)
|
||||
constant f14(14)
|
||||
constant f15(15)
|
||||
constant f16(16)
|
||||
constant f17(17)
|
||||
constant f18(18)
|
||||
constant f19(19)
|
||||
constant f20(20)
|
||||
constant f21(21)
|
||||
constant f22(22)
|
||||
constant f23(23)
|
||||
constant f24(24)
|
||||
constant f25(25)
|
||||
constant f26(26)
|
||||
constant f27(27)
|
||||
constant f28(28)
|
||||
constant f29(29)
|
||||
constant f30(30)
|
||||
constant f31(31)
|
||||
|
||||
// Memory Map
|
||||
constant RDRAM($A000) // $00000000..$003FFFFF RDRAM Memory 4MB ($00000000..$007FFFFF 8MB With Expansion Pak)
|
||||
|
||||
constant RDRAM_BASE($A3F0) // $03F00000..$03F00027 RDRAM Base Register
|
||||
constant RDRAM_DEVICE_TYPE($00) // $03F00000..$03F00003 RDRAM: Device Type Register
|
||||
constant RDRAM_DEVICE_ID($04) // $03F00004..$03F00007 RDRAM: Device ID Register
|
||||
constant RDRAM_DELAY($08) // $03F00008..$03F0000B RDRAM: Delay Register
|
||||
constant RDRAM_MODE($0C) // $03F0000C..$03F0000F RDRAM: Mode Register
|
||||
constant RDRAM_REF_INTERVAL($10) // $03F00010..$03F00013 RDRAM: Ref Interval Register
|
||||
constant RDRAM_REF_ROW($14) // $03F00014..$03F00017 RDRAM: Ref Row Register
|
||||
constant RDRAM_RAS_INTERVAL($18) // $03F00018..$03F0001B RDRAM: Ras Interval Register
|
||||
constant RDRAM_MIN_INTERVAL($1C) // $03F0001C..$03F0001F RDRAM: Minimum Interval Register
|
||||
constant RDRAM_ADDR_SELECT($20) // $03F00020..$03F00023 RDRAM: Address Select Register
|
||||
constant RDRAM_DEVICE_MANUF($24) // $03F00024..$03F00027 RDRAM: Device Manufacturer Register
|
||||
|
||||
constant SP_MEM_BASE($A400) // $04000000..$04000FFF SP MEM Base Register
|
||||
constant SP_DMEM($0000) // $04000000..$04000FFF SP: RSP DMEM (4096 Bytes)
|
||||
constant SP_IMEM($1000) // $04001000..$04001FFF SP: RSP IMEM (4096 Bytes)
|
||||
|
||||
constant SP_BASE($A404) // $04040000..$0404001F SP Base Register
|
||||
constant SP_MEM_ADDR($00) // $04040000..$04040003 SP: Master, SP Memory Address Register
|
||||
constant SP_DRAM_ADDR($04) // $04040004..$04040007 SP: Slave, SP DRAM DMA Address Register
|
||||
constant SP_RD_LEN($08) // $04040008..$0404000B SP: Read DMA Length Register
|
||||
constant SP_WR_LEN($0C) // $0404000C..$0404000F SP: Write DMA Length Register
|
||||
constant SP_STATUS($10) // $04040010..$04040013 SP: Status Register
|
||||
constant SP_DMA_FULL($14) // $04040014..$04040017 SP: DMA Full Register
|
||||
constant SP_DMA_BUSY($18) // $04040018..$0404001B SP: DMA Busy Register
|
||||
constant SP_SEMAPHORE($1C) // $0404001C..$0404001F SP: Semaphore Register
|
||||
|
||||
constant SP_PC_BASE($A408) // $04080000..$04080007 SP PC Base Register
|
||||
constant SP_PC($00) // $04080000..$04080003 SP: PC Register
|
||||
constant SP_IBIST_REG($04) // $04080004..$04080007 SP: IMEM BIST Register
|
||||
|
||||
constant DPC_BASE($A410) // $04100000..$0410001F DP Command (DPC) Base Register
|
||||
constant DPC_START($00) // $04100000..$04100003 DPC: CMD DMA Start Register
|
||||
constant DPC_END($04) // $04100004..$04100007 DPC: CMD DMA End Register
|
||||
constant DPC_CURRENT($08) // $04100008..$0410000B DPC: CMD DMA Current Register
|
||||
constant DPC_STATUS($0C) // $0410000C..$0410000F DPC: CMD Status Register
|
||||
constant DPC_CLOCK($10) // $04100010..$04100013 DPC: Clock Counter Register
|
||||
constant DPC_BUFBUSY($14) // $04100014..$04100017 DPC: Buffer Busy Counter Register
|
||||
constant DPC_PIPEBUSY($18) // $04100018..$0410001B DPC: Pipe Busy Counter Register
|
||||
constant DPC_TMEM($1C) // $0410001C..$0410001F DPC: TMEM Load Counter Register
|
||||
|
||||
constant DPS_BASE($A420) // $04200000..$0420000F DP Span (DPS) Base Register
|
||||
constant DPS_TBIST($00) // $04200000..$04200003 DPS: Tmem Bist Register
|
||||
constant DPS_TEST_MODE($04) // $04200004..$04200007 DPS: Span Test Mode Register
|
||||
constant DPS_BUFTEST_ADDR($08) // $04200008..$0420000B DPS: Span Buffer Test Address Register
|
||||
constant DPS_BUFTEST_DATA($0C) // $0420000C..$0420000F DPS: Span Buffer Test Data Register
|
||||
|
||||
constant MI_BASE($A430) // $04300000..$0430000F MIPS Interface (MI) Base Register
|
||||
constant MI_INIT_MODE($00) // $04300000..$04300003 MI: Init Mode Register
|
||||
constant MI_VERSION($04) // $04300004..$04300007 MI: Version Register
|
||||
constant MI_INTR($08) // $04300008..$0430000B MI: Interrupt Register
|
||||
constant MI_INTR_MASK($0C) // $0430000C..$0430000F MI: Interrupt Mask Register
|
||||
|
||||
constant VI_BASE($A440) // $04400000..$04400037 Video Interface (VI) Base Register
|
||||
constant VI_STATUS($00) // $04400000..$04400003 VI: Status/Control Register
|
||||
constant VI_ORIGIN($04) // $04400004..$04400007 VI: Origin Register
|
||||
constant VI_WIDTH($08) // $04400008..$0440000B VI: Width Register
|
||||
constant VI_V_INTR($0C) // $0440000C..$0440000F VI: Vertical Interrupt Register
|
||||
constant VI_V_CURRENT_LINE($10) // $04400010..$04400013 VI: Current Vertical Line Register
|
||||
constant VI_TIMING($14) // $04400014..$04400017 VI: Video Timing Register
|
||||
constant VI_V_SYNC($18) // $04400018..$0440001B VI: Vertical Sync Register
|
||||
constant VI_H_SYNC($1C) // $0440001C..$0440001F VI: Horizontal Sync Register
|
||||
constant VI_H_SYNC_LEAP($20) // $04400020..$04400023 VI: Horizontal Sync Leap Register
|
||||
constant VI_H_VIDEO($24) // $04400024..$04400027 VI: Horizontal Video Register
|
||||
constant VI_V_VIDEO($28) // $04400028..$0440002B VI: Vertical Video Register
|
||||
constant VI_V_BURST($2C) // $0440002C..$0440002F VI: Vertical Burst Register
|
||||
constant VI_X_SCALE($30) // $04400030..$04400033 VI: X-Scale Register
|
||||
constant VI_Y_SCALE($34) // $04400034..$04400037 VI: Y-Scale Register
|
||||
|
||||
constant AI_BASE($A450) // $04500000..$04500017 Audio Interface (AI) Base Register
|
||||
constant AI_DRAM_ADDR($00) // $04500000..$04500003 AI: DRAM Address Register
|
||||
constant AI_LEN($04) // $04500004..$04500007 AI: Length Register
|
||||
constant AI_CONTROL($08) // $04500008..$0450000B AI: Control Register
|
||||
constant AI_STATUS($0C) // $0450000C..$0450000F AI: Status Register
|
||||
constant AI_DACRATE($10) // $04500010..$04500013 AI: DAC Sample Period Register
|
||||
constant AI_BITRATE($14) // $04500014..$04500017 AI: Bit Rate Register
|
||||
|
||||
constant PI_BASE($A460) // $04600000..$04600033 Peripheral Interface (PI) Base Register
|
||||
constant PI_DRAM_ADDR($00) // $04600000..$04600003 PI: DRAM Address Register
|
||||
constant PI_CART_ADDR($04) // $04600004..$04600007 PI: Pbus (Cartridge) Address Register
|
||||
constant PI_RD_LEN($08) // $04600008..$0460000B PI: Read Length Register
|
||||
constant PI_WR_LEN($0C) // $0460000C..$0460000F PI: Write length register
|
||||
constant PI_STATUS($10) // $04600010..$04600013 PI: Status Register
|
||||
constant PI_BSD_DOM1_LAT($14) // $04600014..$04600017 PI: Domain 1 Latency Register
|
||||
constant PI_BSD_DOM1_PWD($18) // $04600018..$0460001B PI: Domain 1 Pulse Width Register
|
||||
constant PI_BSD_DOM1_PGS($1C) // $0460001C..$0460001F PI: Domain 1 Page Size Register
|
||||
constant PI_BSD_DOM1_RLS($20) // $04600020..$04600023 PI: Domain 1 Release Register
|
||||
constant PI_BSD_DOM2_LAT($24) // $04600024..$04600027 PI: Domain 2 Latency Register
|
||||
constant PI_BSD_DOM2_PWD($28) // $04600028..$0460002B PI: Domain 2 Pulse Width Register
|
||||
constant PI_BSD_DOM2_PGS($2C) // $0460002C..$0460002F PI: Domain 2 Page Size Register
|
||||
constant PI_BSD_DOM2_RLS($30) // $04600030..$04600033 PI: Domain 2 Release Register
|
||||
|
||||
constant RI_BASE($A470) // $04700000..$0470001F RDRAM Interface (RI) Base Register
|
||||
constant RI_MODE($00) // $04700000..$04700003 RI: Mode Register
|
||||
constant RI_CONFIG($04) // $04700004..$04700007 RI: Config Register
|
||||
constant RI_CURRENT_LOAD($08) // $04700008..$0470000B RI: Current Load Register
|
||||
constant RI_SELECT($0C) // $0470000C..$0470000F RI: Select Register
|
||||
constant RI_REFRESH($10) // $04700010..$04700013 RI: Refresh Register
|
||||
constant RI_LATENCY($14) // $04700014..$04700017 RI: Latency Register
|
||||
constant RI_RERROR($18) // $04700018..$0470001B RI: Read Error Register
|
||||
constant RI_WERROR($1C) // $0470001C..$0470001F RI: Write Error Register
|
||||
|
||||
constant SI_BASE($A480) // $04800000..$0480001B Serial Interface (SI) Base Register
|
||||
constant SI_DRAM_ADDR($00) // $04800000..$04800003 SI: DRAM Address Register
|
||||
constant SI_PIF_ADDR_RD64B($04) // $04800004..$04800007 SI: Address Read 64B Register
|
||||
//*RESERVED*($08) // $04800008..$0480000B SI: Reserved Register
|
||||
//*RESERVED*($0C) // $0480000C..$0480000F SI: Reserved Register
|
||||
constant SI_PIF_ADDR_WR64B($10) // $04800010..$04800013 SI: Address Write 64B Register
|
||||
//*RESERVED*($14) // $04800014..$04800017 SI: Reserved Register
|
||||
constant SI_STATUS($18) // $04800018..$0480001B SI: Status Register
|
||||
|
||||
constant CART_DOM2_ADDR1($A500) // $05000000..$0507FFFF Cartridge Domain 2(Address 1) SRAM
|
||||
constant CART_DOM1_ADDR1($A600) // $06000000..$07FFFFFF Cartridge Domain 1(Address 1) 64DD
|
||||
constant CART_DOM2_ADDR2($A800) // $08000000..$0FFFFFFF Cartridge Domain 2(Address 2) SRAM
|
||||
constant CART_DOM1_ADDR2($B000) // $10000000..$18000803 Cartridge Domain 1(Address 2) ROM
|
||||
|
||||
constant PIF_BASE($BFC0) // $1FC00000..$1FC007BF PIF Base Register
|
||||
constant PIF_ROM($000) // $1FC00000..$1FC007BF PIF: Boot ROM
|
||||
constant PIF_RAM($7C0) // $1FC007C0..$1FC007FF PIF: RAM (JoyChannel)
|
||||
constant PIF_HWORD($7C4) // $1FC007C4..$1FC007C5 PIF: HWORD
|
||||
constant PIF_XBYTE($7C6) // $1FC007C6 PIF: Analog X Byte
|
||||
constant PIF_YBYTE($7C7) // $1FC007C7 PIF: Analog Y Byte
|
||||
|
||||
constant CART_DOM1_ADDR3($BFD0) // $1FD00000..$7FFFFFFF Cartridge Domain 1 (Address 3)
|
||||
|
||||
constant EXT_SYS_AD($8000) // $80000000..$FFFFFFFF External SysAD Device
|
||||
|
||||
constant VI_NTSC_CLOCK(48681812) // NTSC: Hz = 48.681812 MHz
|
||||
constant VI_PAL_CLOCK(49656530) // PAL: Hz = 49.656530 MHz
|
||||
constant VI_MPAL_CLOCK(48628316) // MPAL: Hz = 48.628316 MHz
|
||||
|
||||
macro align(size) { // Align Byte Amount
|
||||
while (pc() % {size}) {
|
||||
db 0
|
||||
}
|
||||
}
|
||||
|
||||
macro N64_INIT() {
|
||||
// enables interrupts on SI and PI.
|
||||
// must be done else N64 will stop responding.
|
||||
lui a0,PIF_BASE // A0 = PIF Base Register ($BFC00000)
|
||||
lli t0,8
|
||||
sw t0,PIF_RAM+$3C(a0)
|
||||
}
|
||||
|
||||
macro DMA(start, end, dest) { // DMA Data Copy Cart->DRAM: Start Cart Address, End Cart Address, Destination DRAM Address
|
||||
lui a0,PI_BASE // A0 = PI Base Register ($A4600000)
|
||||
-
|
||||
lw t0,PI_STATUS(a0) // T0 = Word From PI Status Register ($A4600010)
|
||||
andi t0,3 // AND PI Status With 3
|
||||
bnez t0,- // IF TRUE DMA Is Busy
|
||||
nop // Delay Slot
|
||||
|
||||
la t0,{dest}&$7FFFFF // T0 = Aligned DRAM Physical RAM Offset ($00000000..$007FFFFF 8MB)
|
||||
sw t0,PI_DRAM_ADDR(a0) // Store RAM Offset To PI DRAM Address Register ($A4600000)
|
||||
la t0,$10000000|({start}&$3FFFFFF) // T0 = Aligned Cart Physical ROM Offset ($10000000..$13FFFFFF 64MB)
|
||||
sw t0,PI_CART_ADDR(a0) // Store ROM Offset To PI Cart Address Register ($A4600004)
|
||||
la t0,({end}-{start})-1 // T0 = Length Of DMA Transfer In Bytes - 1
|
||||
sw t0,PI_WR_LEN(a0) // Store DMA Length To PI Write Length Register ($A460000C)
|
||||
}
|
||||
523
n64_gfx.inc
Normal file
523
n64_gfx.inc
Normal file
|
|
@ -0,0 +1,523 @@
|
|||
// via krom
|
||||
|
||||
//==============
|
||||
// N64 Graphics
|
||||
//==============
|
||||
constant BPP0($0000) // VI Status/Control: Color Depth Blank (No Data Or Sync) (Bit 0..1)
|
||||
//*RESERVED*($0001) // VI Status/Control: Color Depth Reserved (Bit 0..1)
|
||||
constant BPP16($0002) // VI Status/Control: Color Depth 16BPP R5/G5/B5/A1 (Bit 0..1)
|
||||
constant BPP32($0003) // VI Status/Control: Color Depth 32BPP R8/G8/B8/A8 (Bit 0..1)
|
||||
constant GAMMA_DITHER_EN($00004) // VI Status/Control: Gamma Dither Enable (Requires: Gamma Enable) (Bit 2)
|
||||
constant GAMMA_EN($00008) // VI Status/Control: Gamma Enable (Gamma Boost For YUV Images) (Bit 3)
|
||||
constant DIVOT_EN($00010) // VI Status/Control: Divot Enable (Used With Anti-alias) (Bit 4)
|
||||
constant VBUS_CLK_EN($00020) // VI Status/Control: Video Bus Clock Enable (Bit 5)
|
||||
constant INTERLACE($00040) // VI Status/Control: Interlace/Serrate (Used With Interlaced Display) (Bit 6)
|
||||
constant TST_MODE($00080) // VI Status/Control: Test Mode (Bit 7)
|
||||
constant AA_MODE_0($00000) // VI Status/Control: AA Mode 0 = Anti-alias & Resample (Always Fetch Extra Lines) (Bit 8..9)
|
||||
constant AA_MODE_1($00100) // VI Status/Control: AA Mode 1 = Anti-alias & Resample (Fetch Extra Lines When Needed) (Bit 8..9)
|
||||
constant AA_MODE_2($00200) // VI Status/Control: AA Mode 2 = Resample Only (Bit 8..9)
|
||||
constant AA_MODE_3($00300) // VI Status/Control: AA Mode 3 = Replicate Pixels & No Interpolation (Bit 8..9)
|
||||
constant DIAG_0($00400) // VI Status/Control: Diagnotic 0 (Bit 10..11)
|
||||
constant DIAG_1($00800) // VI Status/Control: Diagnotic 1 (Bit 10..11)
|
||||
constant PIXEL_ADV_0($00000) // VI Status/Control: Pixel Advance 0 (Bit 12..15)
|
||||
constant PIXEL_ADV_1($01000) // VI Status/Control: Pixel Advance 1 (Bit 12..15)
|
||||
constant PIXEL_ADV_2($02000) // VI Status/Control: Pixel Advance 2 (Bit 12..15)
|
||||
constant PIXEL_ADV_3($03000) // VI Status/Control: Pixel Advance 3 (Bit 12..15)
|
||||
constant PIXEL_ADV_4($04000) // VI Status/Control: Pixel Advance 4 (Bit 12..15)
|
||||
constant PIXEL_ADV_5($05000) // VI Status/Control: Pixel Advance 5 (Bit 12..15)
|
||||
constant PIXEL_ADV_6($06000) // VI Status/Control: Pixel Advance 6 (Bit 12..15)
|
||||
constant PIXEL_ADV_7($07000) // VI Status/Control: Pixel Advance 7 (Bit 12..15)
|
||||
constant PIXEL_ADV_8($08000) // VI Status/Control: Pixel Advance 8 (Bit 12..15)
|
||||
constant PIXEL_ADV_9($09000) // VI Status/Control: Pixel Advance 9 (Bit 12..15)
|
||||
constant PIXEL_ADV_A($0A000) // VI Status/Control: Pixel Advance A (Bit 12..15)
|
||||
constant PIXEL_ADV_B($0B000) // VI Status/Control: Pixel Advance B (Bit 12..15)
|
||||
constant PIXEL_ADV_C($0C000) // VI Status/Control: Pixel Advance C (Bit 12..15)
|
||||
constant PIXEL_ADV_D($0D000) // VI Status/Control: Pixel Advance D (Bit 12..15)
|
||||
constant PIXEL_ADV_E($0E000) // VI Status/Control: Pixel Advance E (Bit 12..15)
|
||||
constant PIXEL_ADV_F($0F000) // VI Status/Control: Pixel Advance F (Bit 12..15)
|
||||
constant DITHER_FILTER_EN($10000) // VI Status/Control: Dither Filter Enable (Used With 16BPP Display) (Bit 16)
|
||||
|
||||
macro ScreenNTSC(width,height, status, origin) {
|
||||
lui a0,VI_BASE // A0 = VI Base Register ($A4400000)
|
||||
li t0,{status} // T0 = Status/Control
|
||||
sw t0,VI_STATUS(a0) // Store Status/Control To VI Status Register ($A4400000)
|
||||
la t0,{origin} // T0 = Origin (Frame Buffer Origin In Bytes)
|
||||
sw t0,VI_ORIGIN(a0) // Store Origin To VI Origin Register ($A4400004)
|
||||
lli t0,{width} // T0 = Width (Frame Buffer Line Width In Pixels)
|
||||
sw t0,VI_WIDTH(a0) // Store Width To VI Width Register ($A4400008)
|
||||
lli t0,$200 // T0 = Vertical Interrupt (Interrupt When Current Half-Line $200)
|
||||
sw t0,VI_V_INTR(a0) // Store Vertical Interrupt To VI Interrupt Register ($A440000C)
|
||||
lli t0,0 // T0 = Current Vertical Line (Current Half-Line, Sampled Once Per Line = 0)
|
||||
sw t0,VI_V_CURRENT_LINE(a0) // Store Current Vertical Line To VI Current Register ($A4400010)
|
||||
li t0,$3E52239 // T0 = Video Timing (Start Of Color Burst In Pixels from H-Sync = 3, Vertical Sync Width In Half Lines = 229, Color Burst Width In Pixels = 34, Horizontal Sync Width In Pixels = 57)
|
||||
sw t0,VI_TIMING(a0) // Store Video Timing To VI Burst Register ($A4400014)
|
||||
lli t0,$20D // T0 = Vertical Sync (Number Of Half-Lines Per Field = 525)
|
||||
sw t0,VI_V_SYNC(a0) // Store Vertical Sync To VI V Sync Register ($A4400018)
|
||||
lli t0,$C15 // T0 = Horizontal Sync (5-bit Leap Pattern Used For PAL only = 0, Total Duration Of A Line In 1/4 Pixel = 3093)
|
||||
sw t0,VI_H_SYNC(a0) // Store Horizontal Sync To VI H Sync Register ($A440001C)
|
||||
li t0,$C150C15 // T0 = Horizontal Sync Leap (Identical To H Sync = 3093, Identical To H Sync = 3093)
|
||||
sw t0,VI_H_SYNC_LEAP(a0) // Store Horizontal Sync Leap To VI Leap Register ($A4400020)
|
||||
li t0,$6C02EC // T0 = Horizontal Video (Start Of Active Video In Screen Pixels = 108, End Of Active Video In Screen Pixels = 748)
|
||||
sw t0,VI_H_VIDEO(a0) // Store Horizontal Video To VI H Start Register ($A4400024)
|
||||
li t0,$2501FF // T0 = Vertical Video (Start Of Active Video In Screen Half-Lines = 37, End Of Active Video In Screen Half-Lines = 511)
|
||||
sw t0,VI_V_VIDEO(a0) // Store Vertical Video To VI V Start Register ($A4400028)
|
||||
li t0,$E0204 // T0 = Vertical Burst (Start Of Color Burst Enable In Half-Lines = 14, End Of Color Burst Enable In Half-Lines = 516)
|
||||
sw t0,VI_V_BURST(a0) // Store Vertical Burst To VI V Burst Register ($A440002C)
|
||||
lli t0,($100*({width}/160)) // T0 = X-Scale (Horizontal Subpixel Offset In 2.10 Format = 0, 1/Horizontal Scale Up Factor In 2.10 Format)
|
||||
sw t0,VI_X_SCALE(a0) // Store X-Scale To VI X Scale Register ($A4400030)
|
||||
lli t0,($100*({height}/60)) // T0 = Y-Scale (Vertical Subpixel Offset In 2.10 Format = 0, 1/Vertical Scale Up Factor In 2.10 Format)
|
||||
sw t0,VI_Y_SCALE(a0) // Store Y-Scale To VI Y Scale Register ($A4400034)
|
||||
}
|
||||
|
||||
macro ScreenPAL(width,height, status, origin) {
|
||||
lui a0,VI_BASE // A0 = VI Base Register ($A4400000)
|
||||
li t0,{status} // T0 = Status/Control
|
||||
sw t0,VI_STATUS(a0) // Store Status/Control To VI Status Register ($A4400000)
|
||||
la t0,{origin} // T0 = Origin (Frame Buffer Origin In Bytes)
|
||||
sw t0,VI_ORIGIN(a0) // Store Origin To VI Origin Register ($A4400004)
|
||||
lli t0,{width} // T0 = Width (Frame Buffer Line Width In Pixels)
|
||||
sw t0,VI_WIDTH(a0) // Store Width To VI Width Register ($A4400008)
|
||||
lli t0,$200 // T0 = Vertical Interrupt (Interrupt When Current Half-Line $200)
|
||||
sw t0,VI_V_INTR(a0) // Store Vertical Interrupt To VI Interrupt Register ($A440000C)
|
||||
lli t0,0 // T0 = Current Vertical Line (Current Half-Line, Sampled Once Per Line = 0)
|
||||
sw t0,VI_V_CURRENT_LINE(a0) // Store Current Vertical Line To VI Current Register ($A4400010)
|
||||
li t0,$404233A // T0 = Video Timing (Start Of Color Burst In Pixels from H-Sync = 4, Vertical Sync Width In Half Lines = 04, Color Burst Width In Pixels = 35, Horizontal Sync Width In Pixels = 58)
|
||||
sw t0,VI_TIMING(a0) // Store Video Timing To VI Burst Register ($A4400014)
|
||||
lli t0,$271 // T0 = Vertical Sync (Number Of Half-Lines Per Field = 625)
|
||||
sw t0,VI_V_SYNC(a0) // Store Vertical Sync To VI V Sync Register ($A4400018)
|
||||
li t0,$150C69 // T0 = Horizontal Sync (5-bit Leap Pattern Used For PAL only = 21: %10101, Total Duration Of A Line In 1/4 Pixel = 3177)
|
||||
sw t0,VI_H_SYNC(a0) // Store Horizontal Sync To VI H Sync Register ($A440001C)
|
||||
li t0,$C6F0C6E // T0 = Horizontal Sync Leap (Identical To H Sync = 3183, Identical To H Sync = 3182)
|
||||
sw t0,VI_H_SYNC_LEAP(a0) // Store Horizontal Sync Leap To VI Leap Register ($A4400020)
|
||||
li t0,$800300 // T0 = Horizontal Video (Start Of Active Video In Screen Pixels = 128, End Of Active Video In Screen Pixels = 768)
|
||||
sw t0,VI_H_VIDEO(a0) // Store Horizontal Video To VI H Start Register ($A4400024)
|
||||
li t0,$5F0239 // T0 = Vertical Video (Start Of Active Video In Screen Half-Lines = 95, End Of Active Video In Screen Half-Lines = 569)
|
||||
sw t0,VI_V_VIDEO(a0) // Store Vertical Video To VI V Start Register ($A4400028)
|
||||
li t0,$9026B // T0 = Vertical Burst (Start Of Color Burst Enable In Half-Lines = 9, End Of Color Burst Enable In Half-Lines = 619)
|
||||
sw t0,VI_V_BURST(a0) // Store Vertical Burst To VI V Burst Register ($A440002C)
|
||||
lli t0,($100*({width}/160)) // T0 = X-Scale (Horizontal Subpixel Offset In 2.10 Format = 0, 1/Horizontal Scale Up Factor In 2.10 Format)
|
||||
sw t0,VI_X_SCALE(a0) // Store X-Scale To VI X Scale Register ($A4400030)
|
||||
lli t0,($100*({height}/60)) // T0 = Y-Scale (Vertical Subpixel Offset In 2.10 Format = 0, 1/Vertical Scale Up Factor In 2.10 Format)
|
||||
sw t0,VI_Y_SCALE(a0) // Store Y-Scale To VI Y Scale Register ($A4400034)
|
||||
}
|
||||
|
||||
macro WaitScanline(scanline) { // Wait For RDP To Reach Scanline
|
||||
lui a0,VI_BASE // A0 = VI Base Register ($A4400000)
|
||||
lli t0,{scanline} // T0 = Scan Line
|
||||
-
|
||||
lw t1,VI_V_CURRENT_LINE(a0) // T1 = Current Scan Line
|
||||
bne t1,t0,- // IF (Current Scan Line != Scan Line) Wait
|
||||
nop // ELSE Continue (Delay Slot)
|
||||
}
|
||||
|
||||
// RDP Commands
|
||||
macro DPC(start,end) { // Run DPC Command Buffer: Start Address, End Address
|
||||
lui a0,DPC_BASE // A0 = Reality Display Processer Control Interface Base Register ($A4100000)
|
||||
la a1,{start} // A1 = DPC Command Start Address
|
||||
sw a1,DPC_START(a0) // Store DPC Command Start Address To DP Start Register ($A4100000)
|
||||
la a1,{end} // A1 = DPC Command End Address
|
||||
sw a1,DPC_END(a0) // Store DPC Command End Address To DP End Register ($A4100004)
|
||||
}
|
||||
|
||||
// No_Op: No Effect On RDP Command Execution, Useful For Padding Command Buffers
|
||||
|
||||
// Fill_Triangle: lft,level,tile,yl,ym,yh, xl,xlf,dxldy,dxldyf, xh,xhf,dxhdy,dxhdyf, xm,xmf,dxmdy,dxmdyf
|
||||
// Word 0: Left Major Flag (0=Left Major, 1=Right Major), Number Of Mip-Maps Minus One, Tile ID, Y Coordinate Of Low, Mid Minor, Major Edge (Fixed Point S.11.2)
|
||||
// Word 1: X Coordinate Of Low Edge Integer, Fraction, DxLDy Inverse Slope Of Low Edge Integer, Fraction
|
||||
// Word 2: X Coordinate Of Major Edge Integer, Fraction, DxHDy Inverse Slope Of Major Edge Integer, Fraction
|
||||
// Word 3: X Coordinate Of Middle Edge Integer, Fraction, DxMDy Inverse Slope Of Middle Edge Integer, Fraction
|
||||
|
||||
// Fill_ZBuffer_Triangle: lft,level,tile,yl,ym,yh, xl,xlf,dxldy,dxldyf, xh,xhf,dxhdy,dxhdyf, xm,xmf,dxmdy,dxmdyf
|
||||
// Word 0: Left Major Flag (0=Left Major, 1=Right Major), Number Of Mip-Maps Minus One, Tile ID, Y Coordinate Of Low, Mid Minor, Major Edge (Fixed Point S.11.2)
|
||||
// Word 1: X Coordinate Of Low Edge Integer, Fraction, DxLDy Inverse Slope Of Low Edge Integer, Fraction
|
||||
// Word 2: X Coordinate Of Major Edge Integer, Fraction, DxHDy Inverse Slope Of Major Edge Integer, Fraction
|
||||
// Word 3: X Coordinate Of Middle Edge Integer, Fraction, DxMDy Inverse Slope Of Middle Edge Integer, Fraction
|
||||
// Word 4: Z Inverse Depth Integer, Fraction, DzDx Change In Z Per Change In X Coordinate Integer, Fraction (ZBuffer Coefficients)
|
||||
// Word 5: DzDe Change In Z Along Major Edge Integer, Fraction, DzDy Change In Z Per Change In Y Coordinate Integer, Fraction
|
||||
|
||||
// Texture_Triangle: lft,level,tile,yl,ym,yh, xl,xlf,dxldy,dxldyf, xh,xhf,dxhdy,dxhdyf, xm,xmf,dxmdy,dxmdyf
|
||||
// Word 0: Left Major Flag (0=Left Major, 1=Right Major), Number Of Mip-Maps Minus One, Tile ID, Y Coordinate Of Low, Mid Minor, Major Edge (Fixed Point S.11.2)
|
||||
// Word 1: X Coordinate Of Low Edge Integer, Fraction, DxLDy Inverse Slope Of Low Edge Integer, Fraction
|
||||
// Word 2: X Coordinate Of Major Edge Integer, Fraction, DxHDy Inverse Slope Of Major Edge Integer, Fraction
|
||||
// Word 3: X Coordinate Of Middle Edge Integer, Fraction, DxMDy Inverse Slope Of Middle Edge Integer, Fraction
|
||||
// Word 4: S Texture Coordinate Integer, T Texture Coordinate Integer, W Normalized Inverse Depth Integer (Texture Coefficients)
|
||||
// Word 5: DsDx Change In S, DtDx Change In T, DwDx Change In W Per Change In X Coordinate Integer
|
||||
// Word 6: S Texture Coordinate Fraction, T Texture Coordinate Fraction, W Normalized Inverse Depth Fraction
|
||||
// Word 7: DsDx Change In S, DtDx Change In T, DwDx Change In W Per Change In X Coordinate Fraction
|
||||
// Word 8: DsDe Change In S, DtDe Change In T, DwDe Change In W Along The Edge Integer
|
||||
// Word 9: DsDy Change In S, DtDy Change In T, DwDy Change In W Per Change In Y Coordinate Integer
|
||||
// Word 10: DsDe Change In S, DtDe Change In T, DwDe Change In W Along The Edge Fraction
|
||||
// Word 11: DsDy Change In S, DtDy Change In T, DwDy Change In W Per Change In Y Coordinate Fraction
|
||||
|
||||
// Texture_ZBuffer_Triangle: lft,level,tile,yl,ym,yh, xl,xlf,dxldy,dxldyf, xh,xhf,dxhdy,dxhdyf, xm,xmf,dxmdy,dxmdyf
|
||||
// Word 0: Left Major Flag (0=Left Major, 1=Right Major), Number Of Mip-Maps Minus One, Tile ID, Y Coordinate Of Low, Mid Minor, Major Edge (Fixed Point S.11.2)
|
||||
// Word 1: X Coordinate Of Low Edge Integer, Fraction, DxLDy Inverse Slope Of Low Edge Integer, Fraction
|
||||
// Word 2: X Coordinate Of Major Edge Integer, Fraction, DxHDy Inverse Slope Of Major Edge Integer, Fraction
|
||||
// Word 3: X Coordinate Of Middle Edge Integer, Fraction, DxMDy Inverse Slope Of Middle Edge Integer, Fraction
|
||||
// Word 4: S Texture Coordinate Integer, T Texture Coordinate Integer, W Normalized Inverse Depth Integer (Texture Coefficients)
|
||||
// Word 5: DsDx Change In S, DtDx Change In T, DwDx Change In W Per Change In X Coordinate Integer
|
||||
// Word 6: S Texture Coordinate Fraction, T Texture Coordinate Fraction, W Normalized Inverse Depth Fraction
|
||||
// Word 7: DsDx Change In S, DtDx Change In T, DwDx Change In W Per Change In X Coordinate Fraction
|
||||
// Word 8: DsDe Change In S, DtDe Change In T, DwDe Change In W Along The Edge Integer
|
||||
// Word 9: DsDy Change In S, DtDy Change In T, DwDy Change In W Per Change In Y Coordinate Integer
|
||||
// Word 10: DsDe Change In S, DtDe Change In T, DwDe Change In W Along The Edge Fraction
|
||||
// Word 11: DsDy Change In S, DtDy Change In T, DwDy Change In W Per Change In Y Coordinate Fraction
|
||||
// Word 12: Z Inverse Depth Integer, Fraction, DzDx Change In Z Per Change In X Coordinate Integer, Fraction (ZBuffer Coefficients)
|
||||
// Word 13: DzDe Change In Z Along Major Edge Integer, Fraction, DzDy Change In Z Per Change In Y Coordinate Integer, Fraction
|
||||
|
||||
// Shade_Triangle: lft,level,tile,yl,ym,yh, xl,xlf,dxldy,dxldyf, xh,xhf,dxhdy,dxhdyf, xm,xmf,dxmdy,dxmdyf
|
||||
// Word 0: Left Major Flag (0=Left Major, 1=Right Major), Number Of Mip-Maps Minus One, Tile ID, Y Coordinate Of Low, Mid Minor, Major Edge (Fixed Point S.11.2)
|
||||
// Word 1: X Coordinate Of Low Edge Integer, Fraction, DxLDy Inverse Slope Of Low Edge Integer, Fraction
|
||||
// Word 2: X Coordinate Of Major Edge Integer, Fraction, DxHDy Inverse Slope Of Major Edge Integer, Fraction
|
||||
// Word 3: X Coordinate Of Middle Edge Integer, Fraction, DxMDy Inverse Slope Of Middle Edge Integer, Fraction
|
||||
// Word 4: Red Color Component Integer, Green Color Component Integer, Blue Color Component Integer, Alpha Color Component Integer (Shade Coefficients)
|
||||
// Word 5: DrDx Change In Red, DgDx Change In Green, DbDx Change In Blue, DaDx Change In Alpha Per Change In X Coordinate Integer
|
||||
// Word 6: Red Color Component Fraction, Green Color Component Fraction, Blue Color Component Fraction, Alpha Color Component Fraction
|
||||
// Word 7: DrDx Change In Red, DgDx Change In Green, DbDx Change In Blue, DaDx Change In Alpha Per Change In X Coordinate Fraction
|
||||
// Word 8: DrDe Change In Red, DgDe Change In Green, DbDe Change In Blue, DaDe Change In Alpha Along The Edge Integer
|
||||
// Word 9: DrDy Change In Red, DgDy Change In Green, DbDy Change In Blue, DaDy Change In Alpha Per Change In Y Coordinate Integer
|
||||
// Word 10: DrDe Change In Red, DgDe Change In Green, DbDe Change In Blue, DaDe Change In Alpha Along The Edge Fraction
|
||||
// Word 11: DrDy Change In Red, DgDy Change In Green, DbDy Change In Blue, DaDy Change In Alpha Per Change In Y Coordinate Fraction
|
||||
|
||||
// Shade_ZBuffer_Triangle: lft,level,tile,yl,ym,yh, xl,xlf,dxldy,dxldyf, xh,xhf,dxhdy,dxhdyf, xm,xmf,dxmdy,dxmdyf
|
||||
// Word 0: Left Major Flag (0=Left Major, 1=Right Major), Number Of Mip-Maps Minus One, Tile ID, Y Coordinate Of Low, Mid Minor, Major Edge (Fixed Point S.11.2)
|
||||
// Word 1: X Coordinate Of Low Edge Integer, Fraction, DxLDy Inverse Slope Of Low Edge Integer, Fraction
|
||||
// Word 2: X Coordinate Of Major Edge Integer, Fraction, DxHDy Inverse Slope Of Major Edge Integer, Fraction
|
||||
// Word 3: X Coordinate Of Middle Edge Integer, Fraction, DxMDy Inverse Slope Of Middle Edge Integer, Fraction
|
||||
// Word 4: Red Color Component Integer, Green Color Component Integer, Blue Color Component Integer, Alpha Color Component Integer (Shade Coefficients)
|
||||
// Word 5: DrDx Change In Red, DgDx Change In Green, DbDx Change In Blue, DaDx Change In Alpha Per Change In X Coordinate Integer
|
||||
// Word 6: Red Color Component Fraction, Green Color Component Fraction, Blue Color Component Fraction, Alpha Color Component Fraction
|
||||
// Word 7: DrDx Change In Red, DgDx Change In Green, DbDx Change In Blue, DaDx Change In Alpha Per Change In X Coordinate Fraction
|
||||
// Word 8: DrDe Change In Red, DgDe Change In Green, DbDe Change In Blue, DaDe Change In Alpha Along The Edge Integer
|
||||
// Word 9: DrDy Change In Red, DgDy Change In Green, DbDy Change In Blue, DaDy Change In Alpha Per Change In Y Coordinate Integer
|
||||
// Word 10: DrDe Change In Red, DgDe Change In Green, DbDe Change In Blue, DaDe Change In Alpha Along The Edge Fraction
|
||||
// Word 11: DrDy Change In Red, DgDy Change In Green, DbDy Change In Blue, DaDy Change In Alpha Per Change In Y Coordinate Fraction
|
||||
// Word 12: Z Inverse Depth Integer, Fraction, DzDx Change In Z Per Change In X Coordinate Integer, Fraction (ZBuffer Coefficients)
|
||||
// Word 13: DzDe Change In Z Along Major Edge Integer, Fraction, DzDy Change In Z Per Change In Y Coordinate Integer, Fraction
|
||||
|
||||
// Shade_Texture_Triangle: lft,level,tile,yl,ym,yh, xl,xlf,dxldy,dxldyf, xh,xhf,dxhdy,dxhdyf, xm,xmf,dxmdy,dxmdyf
|
||||
// Word 0: Left Major Flag (0=Left Major, 1=Right Major), Number Of Mip-Maps Minus One, Tile ID, Y Coordinate Of Low, Mid Minor, Major Edge (Fixed Point S.11.2)
|
||||
// Word 1: X Coordinate Of Low Edge Integer, Fraction, DxLDy Inverse Slope Of Low Edge Integer, Fraction
|
||||
// Word 2: X Coordinate Of Major Edge Integer, Fraction, DxHDy Inverse Slope Of Major Edge Integer, Fraction
|
||||
// Word 3: X Coordinate Of Middle Edge Integer, Fraction, DxMDy Inverse Slope Of Middle Edge Integer, Fraction
|
||||
// Word 4: Red Color Component Integer, Green Color Component Integer, Blue Color Component Integer, Alpha Color Component Integer (Shade Coefficients)
|
||||
// Word 5: DrDx Change In Red, DgDx Change In Green, DbDx Change In Blue, DaDx Change In Alpha Per Change In X Coordinate Integer
|
||||
// Word 6: Red Color Component Fraction, Green Color Component Fraction, Blue Color Component Fraction, Alpha Color Component Fraction
|
||||
// Word 7: DrDx Change In Red, DgDx Change In Green, DbDx Change In Blue, DaDx Change In Alpha Per Change In X Coordinate Fraction
|
||||
// Word 8: DrDe Change In Red, DgDe Change In Green, DbDe Change In Blue, DaDe Change In Alpha Along The Edge Integer
|
||||
// Word 9: DrDy Change In Red, DgDy Change In Green, DbDy Change In Blue, DaDy Change In Alpha Per Change In Y Coordinate Integer
|
||||
// Word 10: DrDe Change In Red, DgDe Change In Green, DbDe Change In Blue, DaDe Change In Alpha Along The Edge Fraction
|
||||
// Word 11: DrDy Change In Red, DgDy Change In Green, DbDy Change In Blue, DaDy Change In Alpha Per Change In Y Coordinate Fraction
|
||||
// Word 12: S Texture Coordinate Integer, T Texture Coordinate Integer, W Normalized Inverse Depth Integer (Texture Coefficients)
|
||||
// Word 13: DsDx Change In S, DtDx Change In T, DwDx Change In W Per Change In X Coordinate Integer
|
||||
// Word 14: S Texture Coordinate Fraction, T Texture Coordinate Fraction, W Normalized Inverse Depth Fraction
|
||||
// Word 15: DsDx Change In S, DtDx Change In T, DwDx Change In W Per Change In X Coordinate Fraction
|
||||
// Word 16: DsDe Change In S, DtDe Change In T, DwDe Change In W Along The Edge Integer
|
||||
// Word 17: DsDy Change In S, DtDy Change In T, DwDy Change In W Per Change In Y Coordinate Integer
|
||||
// Word 18: DsDe Change In S, DtDe Change In T, DwDe Change In W Along The Edge Fraction
|
||||
// Word 19: DsDy Change In S, DtDy Change In T, DwDy Change In W Per Change In Y Coordinate Fraction
|
||||
|
||||
// Shade_Texture_Z_Buffer_Triangle: lft,level,tile,yl,ym,yh, xl,xlf,dxldy,dxldyf, xh,xhf,dxhdy,dxhdyf, xm,xmf,dxmdy,dxmdyf
|
||||
// Word 0: Left Major Flag (0=Left Major, 1=Right Major), Number Of Mip-Maps Minus One, Tile ID, Y Coordinate Of Low, Mid Minor, Major Edge (Fixed Point S.11.2)
|
||||
// Word 1: X Coordinate Of Low Edge Integer, Fraction, DxLDy Inverse Slope Of Low Edge Integer, Fraction
|
||||
// Word 2: X Coordinate Of Major Edge Integer, Fraction, DxHDy Inverse Slope Of Major Edge Integer, Fraction
|
||||
// Word 3: X Coordinate Of Middle Edge Integer, Fraction, DxMDy Inverse Slope Of Middle Edge Integer, Fraction
|
||||
// Word 4: Red Color Component Integer, Green Color Component Integer, Blue Color Component Integer, Alpha Color Component Integer (Shade Coefficients)
|
||||
// Word 5: DrDx Change In Red, DgDx Change In Green, DbDx Change In Blue, DaDx Change In Alpha Per Change In X Coordinate Integer
|
||||
// Word 6: Red Color Component Fraction, Green Color Component Fraction, Blue Color Component Fraction, Alpha Color Component Fraction
|
||||
// Word 7: DrDx Change In Red, DgDx Change In Green, DbDx Change In Blue, DaDx Change In Alpha Per Change In X Coordinate Fraction
|
||||
// Word 8: DrDe Change In Red, DgDe Change In Green, DbDe Change In Blue, DaDe Change In Alpha Along The Edge Integer
|
||||
// Word 9: DrDy Change In Red, DgDy Change In Green, DbDy Change In Blue, DaDy Change In Alpha Per Change In Y Coordinate Integer
|
||||
// Word 10: DrDe Change In Red, DgDe Change In Green, DbDe Change In Blue, DaDe Change In Alpha Along The Edge Fraction
|
||||
// Word 11: DrDy Change In Red, DgDy Change In Green, DbDy Change In Blue, DaDy Change In Alpha Per Change In Y Coordinate Fraction
|
||||
// Word 12: S Texture Coordinate Integer, T Texture Coordinate Integer, W Normalized Inverse Depth Integer (Texture Coefficients)
|
||||
// Word 13: DsDx Change In S, DtDx Change In T, DwDx Change In W Per Change In X Coordinate Integer
|
||||
// Word 14: S Texture Coordinate Fraction, T Texture Coordinate Fraction, W Normalized Inverse Depth Fraction
|
||||
// Word 15: DsDx Change In S, DtDx Change In T, DwDx Change In W Per Change In X Coordinate Fraction
|
||||
// Word 16: DsDe Change In S, DtDe Change In T, DwDe Change In W Along The Edge Integer
|
||||
// Word 17: DsDy Change In S, DtDy Change In T, DwDy Change In W Per Change In Y Coordinate Integer
|
||||
// Word 18: DsDe Change In S, DtDe Change In T, DwDe Change In W Along The Edge Fraction
|
||||
// Word 19: DsDy Change In S, DtDy Change In T, DwDy Change In W Per Change In Y Coordinate Fraction
|
||||
// Word 20: Z Inverse Depth Integer, Fraction, DzDx Change In Z Per Change In X Coordinate Integer, Fraction (ZBuffer Coefficients)
|
||||
// Word 21: DzDe Change In Z Along Major Edge Integer, Fraction, DzDy Change In Z Per Change In Y Coordinate Integer, Fraction
|
||||
|
||||
// Shade_Coefficients: r,g,b,a, drdx,dgdx,dbdx,dadx, rf,gf,bf,af, drdxf,dgdxf,dbdxf,dadxf, drde,dgde,dbde,dade, drdy,dgdy,dbdy,dady, drdef,dgdef,dbdef,dadef, drdyf,dgdyf,dbdyf,dadyf
|
||||
// Word 0: Red Color Component Integer, Green Color Component Integer, Blue Color Component Integer, Alpha Color Component Integer (Shade Coefficients)
|
||||
// Word 1: DrDx Change In Red, DgDx Change In Green, DbDx Change In Blue, DaDx Change In Alpha Per Change In X Coordinate Integer
|
||||
// Word 2: Red Color Component Fraction, Green Color Component Fraction, Blue Color Component Fraction, Alpha Color Component Fraction
|
||||
// Word 3: DrDx Change In Red, DgDx Change In Green, DbDx Change In Blue, DaDx Change In Alpha Per Change In X Coordinate Fraction
|
||||
// Word 4: DrDe Change In Red, DgDe Change In Green, DbDe Change In Blue, DaDe Change In Alpha Along The Edge Integer
|
||||
// Word 5: DrDy Change In Red, DgDy Change In Green, DbDy Change In Blue, DaDy Change In Alpha Per Change In Y Coordinate Integer
|
||||
// Word 6: DrDe Change In Red, DgDe Change In Green, DbDe Change In Blue, DaDe Change In Alpha Along The Edge Fraction
|
||||
// Word 7: DrDy Change In Red, DgDy Change In Green, DbDy Change In Blue, DaDy Change In Alpha Per Change In Y Coordinate Fraction
|
||||
|
||||
// Texture_Coefficients: s,t,w, dsdx,dtdx,dwdx, sf,tf,wf, dsdxf,dtdxf,dwdxf, dsde,dtde,dwde, dsdy,dtdy,dwdy, dsdef,dtdef,dwdef, dsdyf,dtdyf,dwdyf
|
||||
// Word 0: S Texture Coordinate Integer, T Texture Coordinate Integer, W Normalized Inverse Depth Integer
|
||||
// Word 1: DsDx Change In S, DtDx Change In T, DwDx Change In W Per Change In X Coordinate Integer
|
||||
// Word 2: S Texture Coordinate Fraction, T Texture Coordinate Fraction, W Normalized Inverse Depth Fraction
|
||||
// Word 3: DsDx Change In S, DtDx Change In T, DwDx Change In W Per Change In X Coordinate Fraction
|
||||
// Word 4: DsDe Change In S, DtDe Change In T, DwDe Change In W Along The Edge Integer
|
||||
// Word 5: DsDy Change In S, DtDy Change In T, DwDy Change In W Per Change In Y Coordinate Integer
|
||||
// Word 6: DsDe Change In S, DtDe Change In T, DwDe Change In W Along The Edge Fraction
|
||||
// Word 7: DsDy Change In S, DtDy Change In T, DwDy Change In W Per Change In Y Coordinate Fraction
|
||||
|
||||
// ZBuffer_Coefficients: z,zf,dzdx,dzdxf, dzde,dzdef,dzdy,dzdyf
|
||||
// Word 0: Z Inverse Depth Integer, Fraction, DzDx Change In Z Per Change In X Coordinate Integer, Fraction (ZBuffer Coefficients)
|
||||
// Word 1: DzDe Change In Z Along Major Edge Integer, Fraction, DzDy Change In Z Per Change In Y Coordinate Integer, Fraction
|
||||
|
||||
// Texture_Rectangle: xl,yl, tile, xh,yh, s,t, dsdx,dtdy
|
||||
// Word 0: Bottom Right X/Y, Tile ID, Top Left X/Y (Fixed Point 10.2)
|
||||
// Word 1: S/T Texture Coordinate Top Left (Fixed Point S.10.5), DsDx Change In S Per Change In X, DtDy Change In T Per Change In Y (Fixed Point S.5.10)
|
||||
|
||||
// Texture_Rectangle_Flip: xl,yl, tile, xh,yh, s,t, dsdx,dtdy ; Same As Texture Rectangle Except Hardware Swaps S/T & DsDx/DtDy
|
||||
// Word 0: Bottom Right X/Y, Tile ID, Top Left X/Y (Fixed Point 10.2)
|
||||
// Word 1: S/T Texture Coordinate Top Left (Fixed Point S.10.5), DsDx Change In S Per Change In X, DtDy Change In T Per Change In Y (Fixed Point S.5.10)
|
||||
|
||||
// Sync_Load: Stall Execution Of Load Commands, Until Preceeding Primitives Completely Finish (Usually Preceed Load Commands)
|
||||
|
||||
// Sync_Pipe: Stall Pipeline, Until Preceeding Primitives Completely Finish (Software Can Optimize Usage)
|
||||
|
||||
// Sync_Tile: Allows Synchronization Between Commands That Write To The Same Tile Descriptor That An Immediately Previous Command Is Reading
|
||||
|
||||
// Sync_Full: Stall RDP Until Last DRAM Buffer Is Read Or Written From Any Preceeding Primitive (Needed If Memory Is To Be Reused)
|
||||
|
||||
// Set_Key_GB: wg,wb,cg,sg,cb,sb ; Set The Coefficients Used For Green/Blue Keying, KEY G/B = CLAMP(0.0, -ABS((G/B - CENTER)* SCALE) + WIDTH, 1.0) KEY ALPHA = MINIMUM OF KEY R/G/B
|
||||
// Word: WIDTH G/B (Size Of Half Key Window Including Soft Edge)*SCALE, CENTER G/B Defines Color Or Intensity At Which Key Is Active (0..255), SCALE GB 1.0/(SIZE OF SOFT EDGE) (0..255)
|
||||
|
||||
// Set_Key_R: wr,cr,sr ; Set The Coefficients Used For Red Keying, KEY R = CLAMP(0.0, -ABS((R - CENTER)* SCALE) + WIDTH, 1.0) KEY ALPHA = MINIMUM OF KEY R/G/B
|
||||
// Word: WIDTH R (Size Of Half Key Window Including Soft Edge)*SCALE, CENTER R Defines Color Or Intensity At Which Key Is Active (0..255), SCALE R 1.0/(SIZE OF SOFT EDGE) (0..255)
|
||||
|
||||
// Set_Convert: k0,k1,k2,k3,k4,k5 ; Updates The Coefficients For Converting YUV Pixels To RGB, R = C0*(Y-16)+C1*V, G = C0*(Y-16)+C2*U-C3*V, B = C0*(Y-16)+C4*U
|
||||
// Word: K0, K1, K2, K3, K4, K5 Term Of YUV-RGB Conversion Matrix
|
||||
|
||||
// Set_Scissor: xh,yh,xl,yl,lo ; Set The Scissoring Of Primitives
|
||||
// Word: Top Left X/Y, Bottom Right X/Y (Fixed Point 10.2), Scissor Field Enable & Scissor Field Even/Odd
|
||||
constant SCISSOR_EVEN(0) // Set_Scissor O: Field Even (Bit 24)
|
||||
constant SCISSOR_ODD(1) // Set_Scissor O: Field Odd (Bit 24)
|
||||
constant SCISSOR_FIELD(1) // Set_Scissor F: Scissor Field Enable (Bit 25)
|
||||
|
||||
// Set_Prim_Depth: pz,pdz ; Set The Depth Of Primitives
|
||||
// Word: Primitive Z Depth, Primitive Delta Z Depth
|
||||
|
||||
// Set_Other_Modes: Settings ; Set The Other Modes
|
||||
// Set_Other_Modes LO Word
|
||||
constant ALPHA_COMPARE_EN($00000000000001) // Set_Other_Modes A: Conditional Color Write On Alpha Compare (Bit 0)
|
||||
constant DITHER_ALPHA_EN($00000000000002) // Set_Other_Modes B: Use Random Noise In Alpha Compare, Otherwise Use Blend Alpha In Alpha Compare (Bit 1)
|
||||
constant Z_SOURCE_SEL($00000000000004) // Set_Other_Modes C: Choose Between Primitive Z And Pixel Z (Bit 2)
|
||||
constant ANTIALIAS_EN($00000000000008) // Set_Other_Modes D: If Not Force Blend, Allow Blend Enable - Use CVG Bits (Bit 3)
|
||||
constant Z_COMPARE_EN($00000000000010) // Set_Other_Modes E: Conditional Color Write Enable On Depth Comparison (Bit 4)
|
||||
constant Z_UPDATE_EN($00000000000020) // Set_Other_Modes F: Enable Writing Of Z If Color Write Enabled (Bit 5)
|
||||
constant IMAGE_READ_EN($00000000000040) // Set_Other_Modes G: Enable Color/CVG Read/Modify/Write Memory Access (Bit 6)
|
||||
constant COLOR_ON_CVG($00000000000080) // Set_Other_Modes H: Only Update Color On Coverage Overflow (Transparent Surfaces) (Bit 7)
|
||||
constant CVG_DEST_CLAMP($00000000000000) // Set_Other_Modes I: CVG Destination Clamp (Normal) (Bit 8..9)
|
||||
constant CVG_DEST_WRAP($00000000000100) // Set_Other_Modes I: CVG Destination Wrap (WAS Assume Full CVG) (Bit 8..9)
|
||||
constant CVG_DEST_ZAP($00000000000200) // Set_Other_Modes I: CVG Destination Zap (Force To Full CVG) (Bit 8..9)
|
||||
constant CVG_DEST_SAVE($00000000000300) // Set_Other_Modes I: CVG Destination Save (Don't Overwrite Memory CVG) (Bit 8..9)
|
||||
constant Z_MODE_OPAQUE($00000000000000) // Set_Other_Modes J: Z Mode Opaque (Bit 10..11)
|
||||
constant Z_MODE_INTERPENETRATING($00000000000400) // Set_Other_Modes J: Z Mode Interpenetrating (Bit 10..11)
|
||||
constant Z_MODE_TRANSPARENT($00000000000800) // Set_Other_Modes J: Z Mode Transparent (Bit 10..11)
|
||||
constant Z_MODE_DECAL($00000000000C00) // Set_Other_Modes J: Z Mode Decal (Bit 10..11)
|
||||
constant CVG_TIMES_ALPHA($00000000001000) // Set_Other_Modes K: Use CVG Times Alpha For Pixel Alpha And Coverage (Bit 12)
|
||||
constant ALPHA_CVG_SELECT($00000000002000) // Set_Other_Modes L: Use CVG (Or CVG*Alpha) For Pixel Alpha (Bit 13)
|
||||
constant FORCE_BLEND($00000000004000) // Set_Other_Modes M: Force Blend Enable (Bit 14)
|
||||
//*RESERVED*($00000000008000) // Set_Other_Modes N: This Mode Bit Is Not Currently Used, But May Be In The Future (Bit 15)
|
||||
constant B_M2B_1_0($00000000000000) // Set_Other_Modes O: Blend Modeword, Multiply 2b Input Select 0, Cycle 1 (Bit 16..17)
|
||||
constant B_M2B_1_1($00000000010000) // Set_Other_Modes O: Blend Modeword, Multiply 2b Input Select 1, Cycle 1 (Bit 16..17)
|
||||
constant B_M2B_1_2($00000000020000) // Set_Other_Modes O: Blend Modeword, Multiply 2b Input Select 2, Cycle 1 (Bit 16..17)
|
||||
constant B_M2B_1_3($00000000030000) // Set_Other_Modes O: Blend Modeword, Multiply 2b Input Select 3, Cycle 1 (Bit 16..17)
|
||||
constant B_M2B_0_0($00000000000000) // Set_Other_Modes P: Blend Modeword, Multiply 2b Input Select 0, Cycle 0 (Bit 18..19)
|
||||
constant B_M2B_0_1($00000000040000) // Set_Other_Modes P: Blend Modeword, Multiply 2b Input Select 1, Cycle 0 (Bit 18..19)
|
||||
constant B_M2B_0_2($00000000080000) // Set_Other_Modes P: Blend Modeword, Multiply 2b Input Select 2, Cycle 0 (Bit 18..19)
|
||||
constant B_M2B_0_3($000000000C0000) // Set_Other_Modes P: Blend Modeword, Multiply 2b Input Select 3, Cycle 0 (Bit 18..19)
|
||||
constant B_M2A_1_0($00000000000000) // Set_Other_Modes Q: Blend Modeword, Multiply 2a Input Select 0, Cycle 1 (Bit 20..21)
|
||||
constant B_M2A_1_1($00000000100000) // Set_Other_Modes Q: Blend Modeword, Multiply 2a Input Select 1, Cycle 1 (Bit 20..21)
|
||||
constant B_M2A_1_2($00000000200000) // Set_Other_Modes Q: Blend Modeword, Multiply 2a Input Select 2, Cycle 1 (Bit 20..21)
|
||||
constant B_M2A_1_3($00000000300000) // Set_Other_Modes Q: Blend Modeword, Multiply 2a Input Select 3, Cycle 1 (Bit 20..21)
|
||||
constant B_M2A_0_0($00000000000000) // Set_Other_Modes R: Blend Modeword, Multiply 2a Input Select 0, Cycle 0 (Bit 22..23)
|
||||
constant B_M2A_0_1($00000000400000) // Set_Other_Modes R: Blend Modeword, Multiply 2a Input Select 1, Cycle 0 (Bit 22..23)
|
||||
constant B_M2A_0_2($00000000800000) // Set_Other_Modes R: Blend Modeword, Multiply 2a Input Select 2, Cycle 0 (Bit 22..23)
|
||||
constant B_M2A_0_3($00000000C00000) // Set_Other_Modes R: Blend Modeword, Multiply 2a Input Select 3, Cycle 0 (Bit 22..23)
|
||||
constant B_M1B_1_0($00000000000000) // Set_Other_Modes S: Blend Modeword, Multiply 1b Input Select 0, Cycle 1 (Bit 24..25)
|
||||
constant B_M1B_1_1($00000001000000) // Set_Other_Modes S: Blend Modeword, Multiply 1b Input Select 1, Cycle 1 (Bit 24..25)
|
||||
constant B_M1B_1_2($00000002000000) // Set_Other_Modes S: Blend Modeword, Multiply 1b Input Select 2, Cycle 1 (Bit 24..25)
|
||||
constant B_M1B_1_3($00000003000000) // Set_Other_Modes S: Blend Modeword, Multiply 1b Input Select 3, Cycle 1 (Bit 24..25)
|
||||
constant B_M1B_0_0($00000000000000) // Set_Other_Modes T: Blend Modeword, Multiply 1b Input Select 0, Cycle 0 (Bit 26..27)
|
||||
constant B_M1B_0_1($00000004000000) // Set_Other_Modes T: Blend Modeword, Multiply 1b Input Select 1, Cycle 0 (Bit 26..27)
|
||||
constant B_M1B_0_2($00000008000000) // Set_Other_Modes T: Blend Modeword, Multiply 1b Input Select 2, Cycle 0 (Bit 26..27)
|
||||
constant B_M1B_0_3($0000000C000000) // Set_Other_Modes T: Blend Modeword, Multiply 1b Input Select 3, Cycle 0 (Bit 26..27)
|
||||
constant B_M1A_1_0($00000000000000) // Set_Other_Modes U: Blend Modeword, Multiply 1a Input Select 0, Cycle 1 (Bit 28..29)
|
||||
constant B_M1A_1_1($00000010000000) // Set_Other_Modes U: Blend Modeword, Multiply 1a Input Select 1, Cycle 1 (Bit 28..29)
|
||||
constant B_M1A_1_2($00000020000000) // Set_Other_Modes U: Blend Modeword, Multiply 1a Input Select 2, Cycle 1 (Bit 28..29)
|
||||
constant B_M1A_1_3($00000030000000) // Set_Other_Modes U: Blend Modeword, Multiply 1a Input Select 3, Cycle 1 (Bit 28..29)
|
||||
constant B_M1A_0_0($00000000000000) // Set_Other_Modes V: Blend Modeword, Multiply 1a Input Select 0, Cycle 0 (Bit 30..31)
|
||||
constant B_M1A_0_1($00000040000000) // Set_Other_Modes V: Blend Modeword, Multiply 1a Input Select 1, Cycle 0 (Bit 30..31)
|
||||
constant B_M1A_0_2($00000080000000) // Set_Other_Modes V: Blend Modeword, Multiply 1a Input Select 2, Cycle 0 (Bit 30..31)
|
||||
constant B_M1A_0_3($000000C0000000) // Set_Other_Modes V: Blend Modeword, Multiply 1a Input Select 3, Cycle 0 (Bit 30..31)
|
||||
// Set_Other_Modes HI Word
|
||||
//*RESERVED*($00000F00000000) // Set_Other_Modes: Reserved For Future Use, Default Value Is $F (Bit 32..35)
|
||||
constant ALPHA_DITHER_SEL_PATTERN($00000000000000) // Set_Other_Modes V1: Alpha Dither Selection Pattern (Bit 36..37)
|
||||
constant ALPHA_DITHER_SEL_PATTERNB($00001000000000) // Set_Other_Modes V1: Alpha Dither Selection ~Pattern (Bit 36..37)
|
||||
constant ALPHA_DITHER_SEL_NOISE($00002000000000) // Set_Other_Modes V1: Alpha Dither Selection Noise (Bit 36..37)
|
||||
constant ALPHA_DITHER_SEL_NO_DITHER($00003000000000) // Set_Other_Modes V1: Alpha Dither Selection No Dither (Bit 36..37)
|
||||
constant RGB_DITHER_SEL_MAGIC_SQUARE_MATRIX($00000000000000) // Set_Other_Modes V2: RGB Dither Selection Magic Square Matrix (Preferred If Filtered) (Bit 38..39)
|
||||
constant RGB_DITHER_SEL_STANDARD_BAYER_MATRIX($00004000000000) // Set_Other_Modes V2: RGB Dither Selection Standard Bayer Matrix (Preferred If Not Filtered) (Bit 38..39)
|
||||
constant RGB_DITHER_SEL_NOISE($00008000000000) // Set_Other_Modes V2: RGB Dither Selection Noise (As Before) (Bit 38..39)
|
||||
constant RGB_DITHER_SEL_NO_DITHER($0000C000000000) // Set_Other_Modes V2: RGB Dither Selection No Dither (Bit 38..39)
|
||||
constant KEY_EN($00010000000000) // Set_Other_Modes W: Enables Chroma Keying (Bit 40)
|
||||
constant CONVERT_ONE($00020000000000) // Set_Other_Modes X: Color Convert Texel That Was The Ouput Of The Texture Filter On Cycle0, Used To Qualify BI_LERP_1 (Bit 41)
|
||||
constant BI_LERP_1($00040000000000) // Set_Other_Modes Y: 1=BI_LERP, 0=Color Convert Operation In Texture Filter. Used In Cycle 1 (Bit 42)
|
||||
constant BI_LERP_0($00080000000000) // Set_Other_Modes Z: 1=BI_LERP, 0=Color Convert Operation In Texture Filter. Used In Cycle 0 (Bit 43)
|
||||
constant MID_TEXEL($00100000000000) // Set_Other_Modes a: Indicates Texture Filter Should Do A 2x2 Half Texel Interpolation, Primarily Used For MPEG Motion Compensation Processing (Bit 44)
|
||||
constant SAMPLE_TYPE($00200000000000) // Set_Other_Modes b: Determines How Textures Are Sampled: 0=1x1 (Point Sample), 1=2x2. Note That Copy (Point Sample 4 Horizontally Adjacent Texels) Mode Is Indicated By CYCLE_TYPE (Bit 45)
|
||||
constant TLUT_TYPE($00400000000000) // Set_Other_Modes c: Type Of Texels In Table, 0=16b RGBA(5/5/5/1), 1=IA(8/8) (Bit 46)
|
||||
constant EN_TLUT($00800000000000) // Set_Other_Modes d: Enable Lookup Of Texel Values From TLUT. Meaningful If Texture Type Is Index, Tile Is In Low TMEM, TLUT Is In High TMEM, And Color Image Is RGB (Bit 47)
|
||||
constant TEX_LOD_EN($01000000000000) // Set_Other_Modes e: Enable Texture Level Of Detail (LOD) (Bit 48)
|
||||
constant SHARPEN_TEX_EN($02000000000000) // Set_Other_Modes f: Enable Sharpened Texture (Bit 49)
|
||||
constant DETAIL_TEX_EN($04000000000000) // Set_Other_Modes g: Enable Detail Texture (Bit 50)
|
||||
constant PERSP_TEX_EN($08000000000000) // Set_Other_Modes h: Enable Perspective Correction On Texture (Bit 51)
|
||||
constant CYCLE_TYPE_1_CYCLE($00000000000000) // Set_Other_Modes i: Display Pipeline Cycle Control Mode 1 Cycle (Bit 52..53)
|
||||
constant CYCLE_TYPE_2_CYCLE($10000000000000) // Set_Other_Modes i: Display Pipeline Cycle Control Mode 2 Cycle (Bit 52..53)
|
||||
constant CYCLE_TYPE_COPY($20000000000000) // Set_Other_Modes i: Display Pipeline Cycle Control Mode Copy (Bit 52..53)
|
||||
constant CYCLE_TYPE_FILL($30000000000000) // Set_Other_Modes i: Display Pipeline Cycle Control Mode Fill (Bit 52..53)
|
||||
//*RESERVED*($40000000000000) // Set_Other_Modes j: This Mode Bit Is Not Currently Used, But May Be In The Future (Bit 54)
|
||||
constant ATOMIC_PRIM($80000000000000) // Set_Other_Modes k: Force Primitive To Be Written To Frame Buffer Before Read Of Following Primitive
|
||||
|
||||
// Load_Tlut: sl,tl,tile,sh,th ; Used To Initiate A Load From DRAM Of An Indexed Texture Lookup Table (TLUT) (This Table Dereferences Color Indexed Texels Before Texture Filtering)
|
||||
// Word: Low S Index Into Table (0..255), Low T Normally Zero, Tile ID, High S Index Into Table, High T Normally Zero (Fixed Point 10.2, Fractional Bits Should Be Zero)
|
||||
|
||||
// Set_Tile_Size: sl,tl,tile,sh,th ; Set The Tile Size
|
||||
// Word: Low S/T Coordinate Of Tile In Image, Tile ID, High S/T Coordinate Of Tile In Image (Fixed Point 10.2)
|
||||
|
||||
// Load_Block: sl,tl,tile,sh,dxt ; Loads A TMEM Tile With A Single Memory "Span" From SL,TL To SH,TL (During Tile Load, T Coordinate Is Incremented By DxT Every 8 TMEM Bytes)
|
||||
// Word: Low S/T Coordinate Of Tile In Image, Tile ID, High S Coordinate Of Tile In Image (Fixed Point 10.2), Unsigned Increment Value
|
||||
|
||||
// Load_Tile: sl,tl,tile,sh,th ; Loads A TMEM Tile
|
||||
// Word: Low S/T Coordinate Of Tile In Image, Tile ID, High S/T Coordinate Of Tile In Image (Fixed Point 10.2)
|
||||
|
||||
// Set_Tile: hi,lo ; Set The Tile
|
||||
// Word: Set Tile Settings
|
||||
// Set_Tile LO Word
|
||||
constant SHIFT_S_0($0) // Set_Tile: Shift 0 Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_1($1) // Set_Tile: Shift 1 Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_2($2) // Set_Tile: Shift 2 Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_3($3) // Set_Tile: Shift 3 Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_4($4) // Set_Tile: Shift 4 Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_5($5) // Set_Tile: Shift 5 Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_6($6) // Set_Tile: Shift 6 Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_7($7) // Set_Tile: Shift 7 Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_8($8) // Set_Tile: Shift 8 Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_9($9) // Set_Tile: Shift 9 Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_A($A) // Set_Tile: Shift A Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_B($B) // Set_Tile: Shift B Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_C($C) // Set_Tile: Shift C Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_D($D) // Set_Tile: Shift D Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_E($E) // Set_Tile: Shift E Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant SHIFT_S_F($F) // Set_Tile: Shift F Level Of Detail Shift For S Addresses (Bit 0..3)
|
||||
constant MASK_S_0($0) // Set_Tile: Mask 0 For Wrapping/Mirroring In S Direction, Zero = Clamp (Bit 14..17)
|
||||
constant MASK_S_1($1) // Set_Tile: Mask 1 For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_2($2) // Set_Tile: Mask 2 For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_3($3) // Set_Tile: Mask 3 For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_4($4) // Set_Tile: Mask 4 For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_5($5) // Set_Tile: Mask 5 For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_6($6) // Set_Tile: Mask 6 For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_7($7) // Set_Tile: Mask 7 For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_8($8) // Set_Tile: Mask 8 For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_9($9) // Set_Tile: Mask 9 For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_A($A) // Set_Tile: Mask A For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_B($B) // Set_Tile: Mask B For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_C($C) // Set_Tile: Mask C For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_D($D) // Set_Tile: Mask D For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_E($E) // Set_Tile: Mask E For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MASK_S_F($F) // Set_Tile: Mask F For Wrapping/Mirroring In S Direction, Pass (Mask) LSBs Of S Address (Bit 4..7)
|
||||
constant MIRROR_S(1) // Set_Tile: Mirror Enable For S Direction (Bit 8)
|
||||
constant CLAMP_S(1) // Set_Tile: Clamp Enable For S Direction (Bit 9)
|
||||
constant SHIFT_T_0($0) // Set_Tile: Shift 0 Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_1($1) // Set_Tile: Shift 1 Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_2($2) // Set_Tile: Shift 2 Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_3($3) // Set_Tile: Shift 3 Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_4($4) // Set_Tile: Shift 4 Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_5($5) // Set_Tile: Shift 5 Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_6($6) // Set_Tile: Shift 6 Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_7($7) // Set_Tile: Shift 7 Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_8($8) // Set_Tile: Shift 8 Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_9($9) // Set_Tile: Shift 9 Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_A($A) // Set_Tile: Shift A Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_B($B) // Set_Tile: Shift B Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_C($C) // Set_Tile: Shift C Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_D($D) // Set_Tile: Shift D Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_E($E) // Set_Tile: Shift E Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant SHIFT_T_F($F) // Set_Tile: Shift F Level Of Detail Shift For T Addresses (Bit 10..13)
|
||||
constant MASK_T_0($0) // Set_Tile: Mask 0 For Wrapping/Mirroring In T Direction, Zero = Clamp (Bit 14..17)
|
||||
constant MASK_T_1($1) // Set_Tile: Mask 1 For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_2($2) // Set_Tile: Mask 2 For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_3($3) // Set_Tile: Mask 3 For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_4($4) // Set_Tile: Mask 4 For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_5($5) // Set_Tile: Mask 5 For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_6($6) // Set_Tile: Mask 6 For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_7($7) // Set_Tile: Mask 7 For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_8($8) // Set_Tile: Mask 8 For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_9($9) // Set_Tile: Mask 9 For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_A($A) // Set_Tile: Mask A For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_B($B) // Set_Tile: Mask B For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_C($C) // Set_Tile: Mask C For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_D($D) // Set_Tile: Mask D For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_E($E) // Set_Tile: Mask E For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MASK_T_F($F) // Set_Tile: Mask F For Wrapping/Mirroring In T Direction, Pass (Mask) LSBs Of T Address (Bit 14..17)
|
||||
constant MIRROR_T(1) // Set_Tile: Mirror Enable For T Direction (Bit 18)
|
||||
constant CLAMP_T(1) // Set_Tile: Clamp Enable For T Direction (Bit 19)
|
||||
constant PALETTE_0($0) // Set_Tile: Palette Number 0 For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_1($1) // Set_Tile: Palette Number 1 For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_2($2) // Set_Tile: Palette Number 2 For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_3($3) // Set_Tile: Palette Number 3 For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_4($4) // Set_Tile: Palette Number 4 For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_5($5) // Set_Tile: Palette Number 5 For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_6($6) // Set_Tile: Palette Number 6 For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_7($7) // Set_Tile: Palette Number 7 For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_8($8) // Set_Tile: Palette Number 8 For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_9($9) // Set_Tile: Palette Number 9 For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_A($A) // Set_Tile: Palette Number A For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_B($B) // Set_Tile: Palette Number B For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_C($C) // Set_Tile: Palette Number C For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_D($D) // Set_Tile: Palette Number D For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_E($E) // Set_Tile: Palette Number E For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
constant PALETTE_F($F) // Set_Tile: Palette Number F For 4Bit Color Indexed Texels, This Number Is The MS 4Bits Of An 8Bit Index (Bit 20..23)
|
||||
// Set_Tile/Set_Texture_Image/Set_Color_Image HI Word
|
||||
constant SIZE_OF_PIXEL_4B(0) // Set_Tile/Set_Texture_Image/Set_Color_Image: Size Of Pixel/Texel Color Element 4B (Bit 51..52)
|
||||
constant SIZE_OF_PIXEL_8B(1) // Set_Tile/Set_Texture_Image/Set_Color_Image: Size Of Pixel/Texel Color Element 8B (Bit 51..52)
|
||||
constant SIZE_OF_PIXEL_16B(2) // Set_Tile/Set_Texture_Image/Set_Color_Image: Size Of Pixel/Texel Color Element 16B (Bit 51..52)
|
||||
constant SIZE_OF_PIXEL_32B(3) // Set_Tile/Set_Texture_Image/Set_Color_Image: Size Of Pixel/Texel Color Element 32B (Bit 51..52)
|
||||
constant IMAGE_DATA_FORMAT_RGBA(0) // Set_Tile/Set_Texture_Image/Set_Color_Image: Image Data Format RGBA (Bit 53..55)
|
||||
constant IMAGE_DATA_FORMAT_YUV(1) // Set_Tile/Set_Texture_Image/Set_Color_Image: Image Data Format YUV (Bit 53..55)
|
||||
constant IMAGE_DATA_FORMAT_COLOR_INDX(2) // Set_Tile/Set_Texture_Image/Set_Color_Image: Image Data Format COLOR_INDX (Bit 53..55)
|
||||
constant IMAGE_DATA_FORMAT_IA(3) // Set_Tile/Set_Texture_Image/Set_Color_Image: Image Data Format IA (Bit 53..55)
|
||||
constant IMAGE_DATA_FORMAT_I(4) // Set_Tile/Set_Texture_Image/Set_Color_Image: Image Data Format I (Bit 53..55)
|
||||
|
||||
// Fill_Rectangle: xl,yl,xh,yh
|
||||
// Word: Bottom Right X/Y, Top Left X/Y (Fixed Point 10.2)
|
||||
|
||||
// Set_Fill_Color: Set The Filling Color
|
||||
// Word: Packed Color: If The Color Image Was Set BE 16B RGBA, Then The Fill Color Would Be Two Horizontally Adjacent 16B RGBA Pixels
|
||||
|
||||
// Set_Fog_Color: Set The Fog Color
|
||||
// Word: RGBA Color Components
|
||||
|
||||
// Set_Blend_Color: Set The Blending Color
|
||||
// Word: RGBA Color Components
|
||||
|
||||
// Set_Prim_Color: minlev,levfrac,lo ; Set The Primitive Color
|
||||
// Word: Prim Min Level: Minimum Clamp For LOD Fraction When In Detail Or Sharpen Texture Modes (Fixed Point 0.5), Prim Level Frac: Level Of Detail Fraction For Primitive, Used Primarily In Multi-Tile Operations For Rectangle Primitives (Fixed Point 0.8), RGBA Color Components
|
||||
|
||||
// Set_Env_Color: Set The Environment Color
|
||||
// Word: RGBA Color Components
|
||||
|
||||
// Set_Combine_Mode: sub_aR0, mulR0, sub_aA0, mulA0, sub_aR1, mulR1, sub_bR0, sub_bR1, sub_aA1, mulA1, addR0, sub_bA0, addA0, addR1, sub_bA1, addA1 ; Set The Combine Mode
|
||||
// Word: SUB_A, Multiply Input RGB Components CYCLE 0, SUB_A, Multiply Input ALPHA Components CYCLE 0, SUB_A, Multiply Input RGB Components CYCLE 1, SUB_B, Multiply Input RGB Components CYCLE 0, SUB_B, Multiply Input RGB Components CYCLE 1, SUB_A, Multiply Input ALPHA Components CYCLE 1, Adder Input RGB Components CYCLE 0, SUB_B Input ALPHA Components CYCLE 0, Adder Input ALPHA Components CYCLE 0, Adder Input RGB Components CYCLE 1, SUB_B Input ALPHA Components CYCLE 1, Adder Input ALPHA Components CYCLE 1
|
||||
|
||||
// Set_Texture_Image: Set The Texture Image
|
||||
// Word: Image Data Format, Size Of Pixel/Texel Color Element, Width Of Image In Pixels - 1, Base Address (Top Left Corner) Of Image In DRAM
|
||||
|
||||
// Set_Z_Image: Set The Z Buffer Image
|
||||
// Word: Base Address (Top Left Corner) Of Image In DRAM, In Bytes
|
||||
|
||||
// Set_Color_Image: Set The Color Image
|
||||
// Word: Image Data Format, Size Of Pixel/Texel Color Element, Width Of Image In Pixels: Image Width=Width+1, Base Address (Top Left Corner) Of Image In DRAM
|
||||
77
xxd.asm
Normal file
77
xxd.asm
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
xxd:
|
||||
// a0: source address
|
||||
// a1: source length
|
||||
// a2: destination (string) address
|
||||
// a3: destination (string) maximum length
|
||||
// v0: error code (0 is OK)
|
||||
beqz a1, xxdExit
|
||||
lli v0, 0 // delay slot
|
||||
lli v1, 0x20 // ascii space
|
||||
|
||||
xxdLoop:
|
||||
lbu t0, 0(a0)
|
||||
subiu a1, a1, 1
|
||||
addiu a0, a0, 1
|
||||
|
||||
// split byte into nybbles
|
||||
srl t1, t0, 4
|
||||
andi t0, t0, 0xF
|
||||
// convert nybbles to ascii bytes
|
||||
sltiu at, t0, 0xA
|
||||
bnez at,+
|
||||
addiu t2, t0, 0x30 // (delay slot)
|
||||
addiu t2, t0, 0x41 - 0xA
|
||||
+
|
||||
sltiu at, t1, 0xA
|
||||
bnez at,+
|
||||
addiu t3, t1, 0x30 // (delay slot)
|
||||
addiu t3, t1, 0x41 - 0xA
|
||||
+
|
||||
|
||||
subiu a3, a3, 3
|
||||
blezl a3, xxdExit
|
||||
lli v0, 1
|
||||
|
||||
sb v1, 0(a2) // write space
|
||||
sb t3, 1(a2) // write high nybble
|
||||
sb t2, 2(a2) // write low nybble
|
||||
addiu a2, a2, 3
|
||||
|
||||
// pretty-printing:
|
||||
andi at, a0, 0xF
|
||||
bnez at,+
|
||||
lli t9, 0x0A // (delay slot) ascii newline
|
||||
subiu a3, a3, 1
|
||||
blezl a3, xxdExit
|
||||
lli v0, 1
|
||||
sb t9, 0(a2) // write newline
|
||||
b ++
|
||||
addiu a2, a2, 1 // delay slot
|
||||
+
|
||||
andi at, a0, 0x3
|
||||
bnez at,+
|
||||
nop // delay slot
|
||||
subiu a3, a3, 1
|
||||
blezl a3, xxdExit
|
||||
lli v0, 1
|
||||
sb v1, 0(a2) // write extra space
|
||||
addiu a2, a2, 1
|
||||
+
|
||||
|
||||
bnez a1, xxdLoop
|
||||
nop // delay slot
|
||||
|
||||
beqz a3, xxdExit
|
||||
nop // delay slot
|
||||
|
||||
xxdZero:
|
||||
// fill the remaining bytes with nulls
|
||||
sb r0, 0(a2)
|
||||
subiu a3, a3, 1
|
||||
bnez a3, xxdZero
|
||||
addiu a2, a2, 1 // delay slot
|
||||
|
||||
xxdExit:
|
||||
jr ra
|
||||
nop // delay slot
|
||||
|
||||
Loading…
Reference in New Issue
Block a user