79 lines
2.3 KiB
NASM
79 lines
2.3 KiB
NASM
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// debug routines for the 64drive, not a real devcart!
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Drive64Write:
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// a0: RAM address to copy from
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// a1: length of data to copy in bytes
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// v0: error code (0 is OK)
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// TODO: a0 should be double-word aligned if used directly with DMA
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// assert a0 (RAM address) is word-aligned
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andi t9, a0, 3
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bnezl t9, Drive64WriteExit
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lli v0, 1
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// assert a1 (copy length) is word-aligned
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andi t9, a1, 3
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bnezl t9, Drive64WriteExit
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lli v0, 2
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blez a1, Drive64WriteExit // nothing to write? nothing to do!
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lli v0, 0 // delay slot
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lui a2, 0x103F // SDRAM destination
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move a3, a1 // SDRAM length
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// flush the cache at a0 to RAM before doing any DMA
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andi t6, a0, 0xF
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addu t7, a0, a1 // stop flushing around here
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subu t6, a0, t6 // align a0 to data line
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subiu t7, t7, 1 // turn inclusive end-point into exclusive instead
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-
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cache 1, 0(t6) // peter says: "Index Writeback Invalidate"
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sltu at, t6, t7
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bnez at,-
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addiu t6, 0x10 // (delay slot) += data line size
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// AND off the DRAM address
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li t9, 0x007FFFFF // __osPiRawStartDma uses 0x1FFFFFFF?
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and t1, a0, t9
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// cart address
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move t2, a2
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// set length (needs to be decremented due to DMA quirk)
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subiu t3, a3, 1
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PI_WAIT()
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sw t1, PI_DRAM_ADDR(t5)
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sw t2, PI_CART_ADDR(t5)
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sw t3, PI_RD_LEN(t5) // "read" from DRAM to cart
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// PI_WAIT() // if we always wait before doing operations, this shouldn't be necessary
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Drive64TestPoint:
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lui at, 0x0100 // set printf channel
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or a3, a3, at
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lli t1, 0x08 // WRITE mode
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// SDRAM parameter is given in multiples of halfwords
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li t9, 0x0FFFFFFF
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and a2, a2, t9
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srl a2, a2, 1
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CI_USB_WRITE_WAIT()
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sw a2, CI_USB_PARAM_RESULT_0(gp)
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PI_WAIT() // yes, these waits seem to be necessary
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sw a3, CI_USB_PARAM_RESULT_1(gp)
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PI_WAIT()
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sw t1, CI_USB_COMMAND_STATUS(gp)
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// CI_USB_WRITE_WAIT() // if we always wait before doing operations, this shouldn't be necessary
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Drive64WriteExit:
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jr ra
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nop // delay slot
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Drive64TestWrite:
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li a2, 0xA0000020
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lli a3, 0x20
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j Drive64TestPoint
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nop // delay slot
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