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add reg# register aliases
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1 changed files with 6 additions and 2 deletions
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@ -30,7 +30,6 @@ local Class = function(inherit)
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return setmetatable(class, mt_class)
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end
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-- TODO: maybe support reg# style too
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local registers = {
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[0]=
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'R0', 'AT', 'V0', 'V1', 'A0', 'A1', 'A2', 'A3',
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@ -77,10 +76,15 @@ revtable(fpu_registers)
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revtable(all_registers)
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revtable(all_directives)
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registers['ZERO'] = 0
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all_registers['ZERO'] = 0
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for i=0, 31 do
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local r = 'REG'..tostring(i)
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registers[r] = i
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all_registers[r] = i
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end
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local fmt_single = 16
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local fmt_double = 17
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local fmt_word = 20
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