108 lines
2.6 KiB
NASM
108 lines
2.6 KiB
NASM
// copy our interrupt handlers into place.
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lui t0, 0x8000
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la t1, _InterruptStart
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la t2, _InterruptEnd
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-
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ld t3, 0(t1)
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ld t4, 8(t1)
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addiu t1, 0x10
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sd t3, 0(t0)
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sd t4, 8(t0)
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cache 0x19, 0(t0) // tell data cache to write itself out
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cache 0x10, 0(t0) // tell instruction cache it needs to reload
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// an instruction cache line is 2 rows, and a data cache line is 1 row,
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// so poking at the start of each row is enough to flush them both.
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bne t1, t2,-
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addiu t0, 0x10
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// flush denormals to 0 and enable invalid operations
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li a0, 0x01000800 // TODO: use flag constants
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ctc1 a0, CP1_FCSR
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// is this just anti-gameshark BS?
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lui a0, 0x0490
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mtc0 a0, CP0_WatchLo
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// initialize the N64 so it doesn't immediately die.
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SI_WAIT()
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lui a0, PIF_BASE
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lw t1, PIF_RAM+0x3C(a0)
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SI_WAIT()
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// the stuff above probably isn't really necessary.
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lli t1, 8
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lui a0, PIF_BASE
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sw t1, PIF_RAM+0x3C(a0)
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// initialize TLB
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lli t1, 0x1E
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lui t2, 0x8000
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mtc0 t2, CP0_EntryHi
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mtc0 r0, CP0_EntryLo0
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mtc0 r0, CP0_EntryLo1
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-
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mtc0 t1, CP0_Index
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nop
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tlbwi
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nop
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nop
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subiu t1, 1
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bgez t1,-
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nop
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mtc0 r0, CP0_EntryHi
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// fill TLB
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lli t1, 0x1F
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mtc0 t1, CP0_Index
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mtc0 r0, CP0_PageMask
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lui t1, 0xC000
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mtc0 t1, CP0_EntryHi
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li t3, 0x02000017
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mtc0 t3, CP0_EntryLo0
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lli t1, 1
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mtc0 t1, CP0_EntryLo1
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nop
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tlbwi
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nop
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nop
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nop
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nop
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mtc0 r0, CP0_EntryHi
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// set BSD DOM1 stuff, whatever that is.
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lui v1, CART_DOM1_ADDR2
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lw v0, 0(v1)
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srl t8, v0, 16
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srl t4, v0, 20
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andi t9, t8, 0xF // t9=$07
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andi t5, t4, 0xF // t5=$03
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srl t7, v0, 8
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//
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andi t7, 0xFF // t7=$12
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andi v0, 0xFF // v0=$40
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// wait for PI
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lui t2, PI_BASE
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-
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lw t0, PI_STATUS(t2)
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andi t0, 3
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bnez t0,-
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nop
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//
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sw v0, PI_BSD_DOM1_LAT(t2) // $40
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sw t9, PI_BSD_DOM1_PGS(t2) // $07
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sw t5, PI_BSD_DOM1_RLS(t2) // $03
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sw t7, PI_BSD_DOM1_PWD(t2) // $12
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// clear DPC counters
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lui a0, DPC_BASE
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lli t0, DPC_TMC_CLR | DPC_PLC_CLR | DPC_CMC_CLR | DPC_CLK_CLR
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sw t0, DPC_STATUS(a0)
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// enable CPU interrupts.
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mfc0 t1, CP0_Status
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ori t1, CP0_STATUS_IM_ALL | CP0_STATUS_IE
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mtc0 t1, CP0_Status
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// enable even more interrupts.
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lui t2, MI_BASE
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lli t0, MI_INTR_MASK_ALL_SET
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sw t0, MI_INTR_MASK(t2)
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