217 lines
5.6 KiB
NASM
217 lines
5.6 KiB
NASM
// built on the N64 ROM template by krom
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arch n64.cpu
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endian msb
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include "n64.inc"
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include "n64_gfx.inc"
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include "64drive.inc"
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output "test.z64", create
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fill 1052672 // Set ROM Size
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origin 0x00000000
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base 0x80000000
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include "header.asm"
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insert "6102.bin"
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// after inserting the header and bootrom,
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// origin should be at 0x1000.
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include "main.inc"
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Start:
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N64_INIT() // enable interrupts
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// SP defaults to RSP instruction memory: 0xA4001FF0
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// we can do better than that.
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lui sp, BLAH_BASE
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// SP should always be 8-byte aligned
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// so that SD and LD instructions don't fail on it.
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subiu sp, sp, 8
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lui s0, BLAH_BASE
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Drive64Init:
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lui gp, CI_BASE
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lui t2, 0x5544 // "UD" of "UDEV"
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lw t1, CI_HW_MAGIC(gp)
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ori t2, t2, 0x4556 // "EV" of "UDEV"
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beq t1, t2, Drive64Confirmed
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nop // delay slot
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Drive64TryExtended:
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lui gp, CI_BASE_EXTENDED
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lw t1, CI_HW_MAGIC(gp)
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bne t1, t2, Main
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nop // delay slot
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Drive64Confirmed:
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sw t2, BLAH_CONFIRMED(s0)
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sw gp, BLAH_CI_BASE(s0)
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// enable writing to cartROM (SDRAM) for USB writing later
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lli t1, 0xF0
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CI_WAIT()
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sw t1, CI_COMMAND(gp) // send our command
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CI_WAIT()
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Main:
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if 0 {
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mfc0 t0, 0x9 // move cycle Count register from COP 0
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sw t0, BLAH_COUNTS+0(s0)
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mfc0 t0, 0x9 // move cycle Count register from COP 0
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sw t0, BLAH_COUNTS+4(s0)
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// seems like 41 half-cycles between the two mfc0's, rarely 42?
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} else {
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mfc0 t0, 0x9
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mfc0 t1, 0x9
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sw t0, BLAH_COUNTS+0(s0)
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sw t1, BLAH_COUNTS+4(s0)
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// seems like 22 half-cycles between the two mfc0's
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}
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// what is our stack pointer set to, anyway?
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sw sp, 0xC(s0)
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// decompress our picture
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include "lz.asm"
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mfc0 t0, 0x9
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sw t0, BLAH_COUNTS+8(s0)
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lw t1, BLAH_CONFIRMED(s0)
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beqz t1, InitVideo
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nop // delay slot
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// jal Drive64TestWrite
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// nop // delay slot
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lui a0, BLAH_BASE
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lli a1, 0x20
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ori a2, a0, BLAH_XXD
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lli a3, 0x20 * 4
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jal xxd
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nop // delay slot
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lui a0, BLAH_BASE // write address
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ori a0, a0, BLAH_XXD // (RAM gets copied to SDRAM by routine)
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lli a1, 0x20 * 4
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jal Drive64Write
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nop // delay slot
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InitVideo: // currently 80001190 (this comment is likely out of date)
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// A4000FC0
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jal LoadRSPBoot
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nop
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lui a0, BLAH_BASE
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jal PushVideoTask
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ori a0, a0, BLAH_SP_TASK
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jal SetupScreen
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nop
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mfc0 t0, 0x9 // move cycle Count register from COP 0
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sw t0, BLAH_COUNTS+0xC(s0)
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MainLoop:
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// borrowing code from krom for now:
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WaitScanline(0x1E0) // Wait For Scanline To Reach Vertical Blank
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WaitScanline(0x1E2)
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// WaitScanline sets a0
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ori t0, r0, 0x00000800 // Even Field
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sw t0, VI_Y_SCALE(a0)
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WaitScanline(0x1E0) // Wait For Scanline To Reach Vertical Blank
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WaitScanline(0x1E2)
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// WaitScanline sets a0
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li t0, 0x02000800 // Odd Field
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sw t0, VI_Y_SCALE(a0)
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j MainLoop
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nop // delay slot
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include "debug.asm" // assumes gp is set to CI base
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SetupScreen:
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// NTSC: 640x480, 32BPP, Interlace, Resample Only, DRAM Origin VIDEO_BUFFER
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ScreenNTSC(640, 480, BPP32|INTERLACE|AA_MODE_2, VIDEO_BUFFER | UNCACHED)
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jr ra
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nop
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LoadRSPBoot:
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li t2, F3DZEX_BOOT
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li t3, F3DZEX_BOOT.size
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subiu t3, t3, 1 // DMA quirk
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SP_DMA_WAIT() // clobbers t0, t5
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ori t1, t5, 0x1000
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sw t1, SP_MEM_ADDR(t5)
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sw t2, SP_DRAM_ADDR(t5)
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sw t3, SP_RD_LEN(t5) // pull data from RDRAM into DMEM/IMEM
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jr ra
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nop
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PushVideoTask:
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// a0: Task RDRAM Pointer (size: 0x40)
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subiu sp, sp, 0x8
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sw ra, 0(sp)
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lli t0, 1 // mode: video
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lli t1, 4 // flags: ???
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li t2, F3DZEX_BOOT
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li t3, F3DZEX_BOOT.size
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li t4, F3DZEX_IMEM & ADDR_MASK
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li t5, F3DZEX_IMEM.size // note: Zelda uses 0x1000 for some reason (0x80 too big).
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li t6, F3DZEX_DMEM & ADDR_MASK
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li t7, F3DZEX_DMEM.size // note: Zelda uses 0x800 for some reason (way too big).
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sw t0, 0x00(a0)
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sw t1, 0x04(a0)
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sw t2, 0x08(a0)
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sw t3, 0x0C(a0)
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sw t4, 0x10(a0)
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sw t5, 0x14(a0)
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sw t6, 0x18(a0)
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sw t7, 0x1C(a0)
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li t0, VIDEO_STACK & ADDR_MASK // ?
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li t1, VIDEO_STACK_SIZE
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li t2, VIDEO_BUFFER & ADDR_MASK
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li t3, (VIDEO_BUFFER & ADDR_MASK) + VIDEO_BUFFER_SIZE // end pointer (not size!)
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li t4, ((BLAH_BASE << 16) | BLAH_DLIST_JUMPER) & ADDR_MASK // initial DList
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lli t5, 8 // size of one jump command
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li t6, VIDEO_YIELD & ADDR_MASK
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li t7, VIDEO_YIELD_SIZE
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sw t0, 0x20(a0)
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sw t1, 0x24(a0)
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sw t2, 0x28(a0)
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sw t3, 0x2C(a0)
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sw t4, 0x30(a0)
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sw t5, 0x34(a0)
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sw t6, 0x38(a0)
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sw t7, 0x3C(a0)
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jal PushRSPTask // a0 passthru
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nop
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lw ra, 0(sp)
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jr ra
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addiu sp, sp, 0x8
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PushRSPTask:
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lli t3, 0x40 - 1 // DMA quirk
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SP_DMA_WAIT() // clobbers t0, t5
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ori t1, t5, 0xFC0
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sw t1, SP_MEM_ADDR(t5)
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sw a0, SP_DRAM_ADDR(t5)
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sw t3, SP_RD_LEN(t5) // pull data from RDRAM into DMEM/IMEM
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jr ra
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nop
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include "xxd.asm"
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align(16); insert F3DZEX_BOOT, "F3DZEX2.boot.bin"
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align(16); insert F3DZEX_DMEM, "F3DZEX2.data.bin"
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align(16); insert F3DZEX_IMEM, "F3DZEX2.bin"
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align(16); insert FONT, "dwarf.1bpp"
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align(16); insert LZ, "Image.lz"
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