Connor Olding
be6a0f8261
unfortunately i seem to have broken console compatibility along the way; it dies after a few frames. i will have to fix this later. for now, i just really need to commit something.
93 lines
3.4 KiB
PHP
93 lines
3.4 KiB
PHP
constant SP_MEM_BASE($A400) // $04000000..$04000FFF SP MEM Base Register
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constant SP_DMEM($0000) // $04000000..$04000FFF SP: RSP DMEM (4096 Bytes)
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constant SP_IMEM($1000) // $04001000..$04001FFF SP: RSP IMEM (4096 Bytes)
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constant SP_BASE($A404) // $04040000..$0404001F SP Base Register
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constant SP_MEM_ADDR($00) // $04040000..$04040003 SP: Master, SP Memory Address Register
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constant SP_DRAM_ADDR($04) // $04040004..$04040007 SP: Slave, SP DRAM DMA Address Register
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constant SP_RD_LEN($08) // $04040008..$0404000B SP: Read DMA Length Register
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constant SP_WR_LEN($0C) // $0404000C..$0404000F SP: Write DMA Length Register
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constant SP_STATUS($10) // $04040010..$04040013 SP: Status Register
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constant SP_DMA_FULL($14) // $04040014..$04040017 SP: DMA Full Register
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constant SP_DMA_BUSY($18) // $04040018..$0404001B SP: DMA Busy Register
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constant SP_SEMAPHORE($1C) // $0404001C..$0404001F SP: Semaphore Register
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constant SP_PC_BASE($A408) // $04080000..$04080007 SP PC Base Register
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constant SP_PC($00) // $04080000..$04080003 SP: PC Register
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constant SP_IBIST_REG($04) // $04080004..$04080007 SP: IMEM BIST Register
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// SP_STATUS Read Flags:
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constant SP_HLT($0001) // Halt
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constant SP_BRK($0002) // Break
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constant SP_BSY($0004) // DMA Busy
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constant SP_FUL($0008) // DMA Full
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constant SP_IOF($0010) // IO Full
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constant SP_STP($0020) // Single Step
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constant SP_IOB($0040) // Interrupt On Break
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constant SP_SG0($0080) // Signal 0 Set
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constant SP_SG1($0100) // Signal 1 Set
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constant SP_SG2($0200) // Signal 2 Set
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constant SP_SG3($0400) // Signal 3 Set
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constant SP_SG4($0800) // Signal 4 Set
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constant SP_SG5($1000) // Signal 5 Set
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constant SP_SG6($2000) // Signal 6 Set
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constant SP_SG7($4000) // Signal 7 Set
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// SP_STATUS Write Flags:
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constant SP_HLT_CLR($00000001) // Clear Halt
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constant SP_HLT_SET($00000002) // Set Halt
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constant SP_BRK_CLR($00000004) // Clear Broke
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constant SP_INT_CLR($00000008) // Clear Interrupt
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constant SP_INT_SET($00000010) // Set Interrupt
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constant SP_STP_CLR($00000020) // Clear Single Step
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constant SP_STP_SET($00000040) // Set Single Step
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constant SP_IOB_CLR($00000080) // Clear Interrupt On Break
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constant SP_IOB_SET($00000100) // Set Interrupt On Break
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constant SP_SG0_CLR($00000200) // Clear Signal 0
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constant SP_SG0_SET($00000400) // Set Signal 0
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constant SP_SG1_CLR($00000800) // Clear Signal 1
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constant SP_SG1_SET($00001000) // Set Signal 1
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constant SP_SG2_CLR($00002000) // Clear Signal 2
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constant SP_SG2_SET($00004000) // Set Signal 2
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constant SP_SG3_CLR($00008000) // Clear Signal 3
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constant SP_SG3_SET($00010000) // Set Signal 3
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constant SP_SG4_CLR($00020000) // Clear Signal 4
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constant SP_SG4_SET($00040000) // Set Signal 4
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constant SP_SG5_CLR($00080000) // Clear Signal 5
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constant SP_SG5_SET($00100000) // Set Signal 5
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constant SP_SG6_CLR($00200000) // Clear Signal 6
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constant SP_SG6_SET($00400000) // Set Signal 6
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constant SP_SG7_CLR($00800000) // Clear Signal 7
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constant SP_SG7_SET($01000000) // Set Signal 7
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macro SP_DMA_WAIT() { // from CPU
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lui t5, SP_BASE
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-
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lw t0, SP_DMA_FULL(t5)
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bnez t0,-
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nop
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-
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lw t0, SP_DMA_BUSY(t5)
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bnez t0,-
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nop
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}
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macro SP_BUSY_WAIT() {
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lui a0, SP_BASE
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-
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lw t0, SP_STATUS(a0)
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andi t0, 0x1C
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sltu t0, r0, t0
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bnez t0,-
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nop
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}
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macro SP_WAIT() {
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lui a0, SP_BASE
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-
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lw t0, SP_STATUS(a0)
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andi t0, 1
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beqz t0,-
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nop
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}
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