331 lines
7.3 KiB
NASM
331 lines
7.3 KiB
NASM
Drive64Write:
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// a0: RAM address to copy from
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// a1: length of data to copy in bytes
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// v0: error code (0 is OK)
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// TODO: a0 should be double-word aligned if used directly with DMA
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// assert a0 (RAM address) is word-aligned
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andi t9, a0, 3
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bnez t9, Drive64WriteExit
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lli v0, 1
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// assert a1 (copy length) is word-aligned
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andi t9, a1, 3
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bnez t9, Drive64WriteExit
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lli v0, 2
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blez a1, Drive64WriteExit // nothing to write? nothing to do!
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lli v0, 0
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lui t0, K_BASE
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lw t1, K_CONSOLE_AVAILABLE(t0)
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beqz t1, Drive64WriteExit
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lli v0, 0
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lui a2, 0x103F // SDRAM destination
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move a3, a1 // SDRAM length
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// flush the cache at a0 to RAM before doing any DMA
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andi t6, a0, 0xF
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addu t7, a0, a1 // stop flushing around here
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subu t6, a0, t6 // align a0 to data line
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-
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cache 1, 0(t6) // data cache Index Writeback Invalidate
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addiu t6, 0x10 // += data line size
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sltu at, t6, t7
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bnez at,-
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nop
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// AND off the DRAM address
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li t9, 0x007FFFFF // __osPiRawStartDma uses 0x1FFFFFFF?
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and t1, a0, t9
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// cart address
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or t2, a2, r0
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// set length (needs to be decremented due to DMA quirk)
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subiu t3, a3, 1
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PI_WAIT() // clobbers a0,t0
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sw t1, PI_DRAM_ADDR(a0)
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sw t2, PI_CART_ADDR(a0)
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sw t3, PI_RD_LEN(a0) // "read" from DRAM to cart
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PI_WAIT()
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Drive64WriteDirect: // TODO: rewrite so this takes a0,a1 instead of a2,a3
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lli v0, 0
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lui at, 0x0100 // set printf channel
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or a3, a3, at
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lli t1, 0x08 // WRITE mode
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// SDRAM parameter is given in multiples of halfwords
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li t9, 0x0FFFFFFF
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and a2, a2, t9
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srl a2, a2, 1
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lui t9, K_BASE
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lw t9, K_CI_BASE(t9)
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CI_USB_WRITE_WAIT(0x10000) // clobbers a0,v0,t0, requires t9
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bnez v0, Drive64WriteExit
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nop
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sw a2, CI_USB_PARAM_RESULT_0(t9)
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PI_WAIT() // yes, these waits seem to be necessary
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sw a3, CI_USB_PARAM_RESULT_1(t9)
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PI_WAIT()
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sw t1, CI_USB_COMMAND_STATUS(t9)
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CI_USB_WRITE_WAIT(0x10000) // clobbers a0,v0,t0, requires t9
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Drive64WriteExit:
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jr ra
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nop
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Drive64TestWrite:
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li a2, 0xA0000020
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lli a3, 0x20
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j Drive64WriteDirect
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nop
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include "xxd.asm"
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DumpAndWrite:
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// a0: source address
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// a1: source length
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// a2: temp string address
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// a3: temp string maximum length
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// v0: error code (0 is OK)
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subiu sp, sp, 0x20
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sw ra, 0x10(sp)
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// TODO: can i just use the a0,a1,a2,a3 slots here?
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sw s0, 0x14(sp)
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sw s1, 0x18(sp)
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or s0, a2, r0
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jal xxd
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or s1, a3, r0
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bnez v0, DumpAndWriteExit
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or a0, s0, r0 // delay slot
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jal Drive64Write
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or a1, s1, r0
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// v0 passthru
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DumpAndWriteExit:
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lw ra, 0x10(sp)
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lw s0, 0x14(sp)
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lw s1, 0x18(sp)
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jr ra
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addiu sp, sp, 0x20
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DumpRegisters:
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// NOTE: only use this in ISR_Main
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// a0: temp string address
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// a1: temp string maximum length
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// v0: error code (0 is OK)
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// TODO: 64-bit variant
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subiu sp, 0x30
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sw ra, 0x10(sp)
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sw s0, 0x14(sp)
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sw s1, 0x18(sp)
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sw s2, 0x1C(sp)
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sw s3, 0x20(sp)
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slti at, a1, (4 + 8 + 1) * 34 + 1 // = 443
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bnez at, DumpRegistersExit
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lli v0, 1
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la s0, DumpRegistersStrings
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lui s1, K_BASE
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macro DumpReg(offset) {
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lb t1, 0(s0)
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lb t2, 1(s0)
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lb t3, 2(s0)
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lb t4, 3(s0)
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sb t1, 0(a0)
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sb t2, 1(a0)
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sb t3, 2(a0)
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sb t4, 3(a0)
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addiu a0, 4
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jal DumpRegistersHelper // a0 passthru
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lw a1, K_DUMP+{offset}+4(s1)
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or a0, v0, r0
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}
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lli s2, 0x20 // ascii space
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lli s3, 0x0A // ascii newline
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define DR_i(0)
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while {DR_i} < 16 {
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DumpReg({DR_i} * 8)
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sb s2, 0(a0)
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addiu a0, 1
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addiu s0, 16 * 4
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DumpReg({DR_i} * 8 + 0x80)
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sb s3, 0(a0)
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addiu a0, 1
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subiu s0, 16 * 4 - 4
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evaluate DR_i({DR_i} + 1)
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}
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// dump HI and LO separately
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addiu s0, 16 * 4
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DumpReg(32 * 8)
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sb s2, 0(a0)
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addiu a0, 1
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addiu s0, 4
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DumpReg(33 * 8)
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sb s3, 0(a0)
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addiu a0, 1
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sb r0, 0(a0) // null-terminate
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lli v0, 0
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DumpRegistersExit:
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lw ra, 0x10(sp)
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lw s0, 0x14(sp)
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lw s1, 0x18(sp)
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lw s2, 0x1C(sp)
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lw s3, 0x20(sp)
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jr ra
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addiu sp, 0x20
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DumpRegistersHelper:
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// a0: output pointer
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// a1: 32-bit value to dump
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// v0: new output pointer
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andi t1, a1, 0xF
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srl t2, a1, 4
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andi t2, t2, 0xF
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srl t3, a1, 8
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andi t3, t3, 0xF
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srl t4, a1, 12
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andi t4, t4, 0xF
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srl t5, a1, 16
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andi t5, t5, 0xF
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srl t6, a1, 20
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andi t6, t6, 0xF
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srl t7, a1, 24
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andi t7, t7, 0xF
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srl t8, a1, 28
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macro AsciiNybble(reg, out) {
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sltiu at, {reg}, 0xA
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bnez at,+
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addiu {out}, {reg}, 0x30 // delay slot
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addiu {out}, {reg}, 0x41 - 0xA
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+
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}
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AsciiNybble(t8, v0)
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sb v0, 0(a0)
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AsciiNybble(t7, v0)
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sb v0, 1(a0)
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AsciiNybble(t6, v0)
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sb v0, 2(a0)
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AsciiNybble(t5, v0)
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sb v0, 3(a0)
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AsciiNybble(t4, v0)
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sb v0, 4(a0)
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AsciiNybble(t3, v0)
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sb v0, 5(a0)
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AsciiNybble(t2, v0)
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sb v0, 6(a0)
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AsciiNybble(t1, v0)
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sb v0, 7(a0)
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jr ra
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addiu v0, a0, 8
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// each string is assumed to be 4 bytes long
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DumpRegistersStrings:
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db "r0: ", "at: ", "v0: ", "v1: "
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db "a0: ", "a1: ", "a2: ", "a3: "
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db "t0: ", "t1: ", "t2: ", "t3: "
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db "t4: ", "t5: ", "t6: ", "t7: "
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db "s0: ", "s1: ", "s2: ", "s3: "
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db "s4: ", "s5: ", "s6: ", "s7: "
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db "t8: ", "t9: ", "k0: ", "k1: "
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db "gp: ", "sp: ", "fp: ", "ra: "
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db "HI: ", "LO: "
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DumpWord:
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// a0: address of word to dump
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subiu sp, 0x18
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sw ra, 0x10(sp)
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sw s0, 0x14(sp)
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move s0, a0
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la a0, DumpWordString
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jal DumpRegistersHelper
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move a1, s0
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la a0, DumpWordString + 12
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jal DumpRegistersHelper
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lw a1, 0(s0)
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la a0, DumpWordString
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jal Drive64Write
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lli a1, 24
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lw ra, 0x10(sp)
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lw s0, 0x14(sp)
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jr ra
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addiu sp, 0x18
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align(8)
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DumpWordString:
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db "........: ........\n", 0, 0, 0
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align(8)
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PokeDataCache:
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lui a0, 0x8000
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ori a1, a0, 8 * 1024 // cache size
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-
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cache 1, 0x00(a0)
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cache 1, 0x10(a0)
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cache 1, 0x20(a0)
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cache 1, 0x30(a0)
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cache 1, 0x40(a0)
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cache 1, 0x50(a0)
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cache 1, 0x60(a0)
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cache 1, 0x70(a0)
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addiu a0, 0x80
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bne a0, a1,-
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nop
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jr ra
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nop
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PokeInstrCache:
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lui a0, 0x8000
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ori a1, a0, 16 * 1024 // cache size
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-
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cache 0, 0x00(a0)
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cache 0, 0x20(a0)
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cache 0, 0x40(a0)
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cache 0, 0x60(a0)
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cache 0, 0x80(a0)
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cache 0, 0xA0(a0)
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cache 0, 0xC0(a0)
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cache 0, 0xE0(a0)
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addiu a0, 0x100
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bne a0, a1,-
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nop
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jr ra
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nop
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PokeCaches:
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subiu sp, 0x18
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sw ra, 0x10(sp)
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jal PokeDataCache
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nop
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jal PokeInstrCache
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nop
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lw ra, 0x10(sp)
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jr ra
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addiu sp, 0x18
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