reorganize constants and macros
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20 changed files with 555 additions and 585 deletions
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@ -44,7 +44,7 @@ if {dpos} >= 0x8000 {
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// sets alpha component to 8, everything else to 0
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// sets alpha component to 8, everything else to 0
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WriteDL(0xF9000000, 0x00000008)
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WriteDL(0xF9000000, 0x00000008)
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// sets near-far plane clipping? maybe?
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// sets near- far-plane clipping? maybe?
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// G_MOVEWORD, sets G_MW_CLIP+$0004
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// G_MOVEWORD, sets G_MW_CLIP+$0004
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WriteDL(0xDB040004, 2)
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WriteDL(0xDB040004, 2)
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// G_MOVEWORD, sets G_MW_CLIP+$000C
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// G_MOVEWORD, sets G_MW_CLIP+$000C
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34
inc/main.inc
34
inc/main.inc
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@ -1,10 +1,6 @@
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// settings:
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// settings:
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constant K_DEBUG(1) // slows down interrupt handling to enable debug routines
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constant K_DEBUG(1) // slows down interrupt handling to enable debug routines
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// address stuff:
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constant UNCACHED(0xA0000000)
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constant ADDR_MASK(0x1FFFFFFF)
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constant BLAH_BASE(0x803F)
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constant BLAH_BASE(0x803F)
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constant BLAH_COUNTS(0x0010)
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constant BLAH_COUNTS(0x0010)
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constant BLAH_SP_TASK(0x0040)
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constant BLAH_SP_TASK(0x0040)
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@ -22,33 +18,3 @@ constant VIDEO_STACK(VIDEO_SOMETHING + VIDEO_SOMETHING_SIZE)
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constant VIDEO_STACK_SIZE(0x400)
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constant VIDEO_STACK_SIZE(0x400)
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constant VIDEO_YIELD(VIDEO_STACK + VIDEO_STACK_SIZE)
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constant VIDEO_YIELD(VIDEO_STACK + VIDEO_STACK_SIZE)
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constant VIDEO_YIELD_SIZE(0xC00)
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constant VIDEO_YIELD_SIZE(0xC00)
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macro nops(new_pc) {
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if (pc() > {new_pc}) {
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error "PC is already past the point specified"
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}
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while (pc() < {new_pc}) {
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nop
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}
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}
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macro PI_WAIT() {
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lui t5, PI_BASE
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-
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lw t0, PI_STATUS(t5)
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andi t0, t0, 3
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bnez t0,-
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nop
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}
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macro SP_DMA_WAIT() { // from CPU
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lui t5, SP_BASE
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-
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lw t0, SP_DMA_FULL(t5)
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bnez t0,-
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nop
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-
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lw t0, SP_DMA_BUSY(t5)
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bnez t0,-
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nop
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}
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427
inc/n64.inc
427
inc/n64.inc
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@ -1,209 +1,21 @@
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// by krom, edited by notwa
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// by krom, expanded and reorganized by notwa
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//=============
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include "n64_cpu.inc"
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// N64 Include
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include "n64_cop0.inc"
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//=============
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include "n64_cop1.inc"
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// N64 MIPS 4300 CPU Registers
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include "n64_map.inc"
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constant r0(0)
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include "n64_sp.inc"
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constant r1(1)
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include "n64_dp.inc"
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constant r2(2)
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include "n64_mi.inc"
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constant r3(3)
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include "n64_vi.inc"
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constant r4(4)
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include "n64_ai.inc"
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constant r5(5)
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include "n64_pi.inc"
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constant r6(6)
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include "n64_ri.inc"
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constant r7(7)
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include "n64_si.inc"
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constant r8(8)
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include "n64_pif.inc"
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constant r9(9)
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include "n64_util.inc"
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constant r10(10)
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constant r11(11)
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constant r12(12)
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constant r13(13)
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constant r14(14)
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constant r15(15)
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constant r16(16)
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constant r17(17)
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constant r18(18)
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constant r19(19)
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constant r20(20)
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constant r21(21)
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constant r22(22)
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constant r23(23)
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constant r24(24)
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constant r25(25)
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constant r26(26)
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constant r27(27)
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constant r28(28)
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constant r29(29)
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constant r30(30)
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constant r31(31)
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constant at(1)
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constant v0(2)
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constant v1(3)
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constant a0(4)
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constant a1(5)
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constant a2(6)
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constant a3(7)
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constant t0(8)
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constant t1(9)
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constant t2(10)
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constant t3(11)
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constant t4(12)
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constant t5(13)
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constant t6(14)
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constant t7(15)
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constant s0(16)
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constant s1(17)
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constant s2(18)
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constant s3(19)
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constant s4(20)
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constant s5(21)
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constant s6(22)
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constant s7(23)
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constant t8(24)
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constant t9(25)
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constant k0(26)
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constant k1(27)
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constant gp(28)
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constant sp(29)
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constant fp(30)
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constant ra(31)
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constant s8(30) // alias of fp
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// N64 MIPS 4300 CP1 Floating Point Unit (FPU) Registers (COP1)
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constant f0(0)
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constant f1(1)
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constant f2(2)
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constant f3(3)
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constant f4(4)
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constant f5(5)
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constant f6(6)
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constant f7(7)
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constant f8(8)
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constant f9(9)
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constant f10(10)
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constant f11(11)
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constant f12(12)
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constant f13(13)
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constant f14(14)
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constant f15(15)
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constant f16(16)
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constant f17(17)
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constant f18(18)
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constant f19(19)
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constant f20(20)
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constant f21(21)
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constant f22(22)
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constant f23(23)
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constant f24(24)
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constant f25(25)
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constant f26(26)
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constant f27(27)
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constant f28(28)
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constant f29(29)
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constant f30(30)
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constant f31(31)
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// Coprocessor 0 registers
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constant CP0_Index(0)
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constant CP0_Random(1)
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constant CP0_EntryLo0(2)
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constant CP0_EntryLo1(3)
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constant CP0_Context(4)
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constant CP0_PageMask(5)
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constant CP0_Wired(6)
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constant CP0_Reserved_1(7)
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constant CP0_BadVAddr(8)
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constant CP0_Count(9)
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constant CP0_EntryHi(10)
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constant CP0_Compare(11)
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constant CP0_Status(12)
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constant CP0_Cause(13)
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constant CP0_EPC(14)
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constant CP0_PRid(15)
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constant CP0_Config(16)
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constant CP0_LLAddr(17)
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constant CP0_WatchLo(18)
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constant CP0_WatchHi(19)
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constant CP0_XContext(20)
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constant CP0_Reserved_2(21)
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constant CP0_Reserved_3(22)
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constant CP0_Reserved_4(23)
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constant CP0_Reserved_5(24)
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constant CP0_Reserved_6(25)
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constant CP0_PErr(26) // unused
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constant CP0_CacheErr(27) // unused
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constant CP0_TagLo(28)
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constant CP0_TagHi(29) // reserved
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constant CP0_ErrorPC(30)
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constant CP0_Reserved_7(31)
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constant CP0_STATUS_IE($0001) // Interrupt Enable
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constant CP0_STATUS_EXL($0002) // Exception Level
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constant CP0_STATUS_ERL($0004) // Error Level
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constant CP0_STATUS_IM0($0100) // Interrupt Mask 0 (Software)
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constant CP0_STATUS_IM1($0200) // Interrupt Mask 1 (Software)
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constant CP0_STATUS_IM2($0400) // Interrupt Mask 2 (External)
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constant CP0_STATUS_IM3($0800) // Interrupt Mask 3 (External)
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constant CP0_STATUS_IM4($1000) // Interrupt Mask 4 (External)
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constant CP0_STATUS_IM5($2000) // Interrupt Mask 5 (External)
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constant CP0_STATUS_IM6($4000) // Interrupt Mask 6 (External)
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constant CP0_STATUS_IM7($8000) // Interrupt Mask 7 (External)
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constant CP0_STATUS_IM_ALL($FF01) // enable all interrupts
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// note that these are all masks.
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constant CP0_CAUSE_CODE($007C) // actually supposed to be called ExcCode
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constant CP0_CAUSE_IP0($0100) // Interrupt Pending 0 (Software)
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constant CP0_CAUSE_IP1($0200) // Interrupt Pending 1 (Software)
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constant CP0_CAUSE_IP2($0400) // Interrupt Pending 2 (External)
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constant CP0_CAUSE_IP3($0800) // Interrupt Pending 3 (External)
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constant CP0_CAUSE_IP4($1000) // Interrupt Pending 4 (External)
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constant CP0_CAUSE_IP5($2000) // Interrupt Pending 5 (External)
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constant CP0_CAUSE_IP6($4000) // Interrupt Pending 6 (External)
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constant CP0_CAUSE_IP7($8000) // Interrupt Pending 7 (External)
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// upper halfword:
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constant CP0_CAUSE_CE($30000000) // Coprocessor Error
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constant CP0_CAUSE_BD($80000000) // Branch Delay (not an exception, just info)
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// note that these constants are shifted left 2 into the Cause register,
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// so you must unshift the value from the register before comparing them.
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constant CP0_CODE_INT(0) // Interrupt
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constant CP0_CODE_MOD(1) // TLB modification exception
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constant CP0_CODE_TLBL(2) // TLB Exception (Load or instruction fetch)
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constant CP0_CODE_TLBS(3) // TLB Exception (Store)
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constant CP0_CODE_ADEL(4) // Address Error Exception (Load or instruction fetch)
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constant CP0_CODE_ADES(5) // Address Error Exception (Store)
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constant CP0_CODE_IBE(6) // Bus Error Exception (instruction fetch)
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constant CP0_CODE_DBE(7) // Bus Error Exception (data reference: load or store)
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constant CP0_CODE_SYS(8) // SysCall Exception
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constant CP0_CODE_BP(9) // Breakpoint Exception
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constant CP0_CODE_RI(10) // Reserved instruction Exception
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constant CP0_CODE_CPU(11) // Coprocessor Unusable Exception
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constant CP0_CODE_OV(12) // Arithmetic Overflow Exception
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constant CP0_CODE_TR(13) // Trap Exception
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constant CP0_CODE_RESERVED_14(14)
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constant CP0_CODE_FPE(15) // Floating Point Exception
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constant CP0_CODE_RESERVED_16(16)
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constant CP0_CODE_RESERVED_17(17)
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constant CP0_CODE_RESERVED_18(18)
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constant CP0_CODE_RESERVED_19(19)
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constant CP0_CODE_RESERVED_20(20)
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constant CP0_CODE_RESERVED_21(21)
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constant CP0_CODE_RESERVED_22(22)
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constant CP0_CODE_WATCH(23) // Reference to WatchHi/WatchLo address
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constant CP0_CODE_RESERVED_24(24)
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constant CP0_CODE_RESERVED_25(25)
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constant CP0_CODE_RESERVED_26(26)
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constant CP0_CODE_RESERVED_27(27)
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constant CP0_CODE_RESERVED_28(28)
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constant CP0_CODE_RESERVED_29(29)
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constant CP0_CODE_RESERVED_30(30)
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constant CP0_CODE_RESERVED_31(31)
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// Memory Map
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// Memory Map
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constant RDRAM($A000) // $00000000..$003FFFFF RDRAM Memory 4MB ($00000000..$007FFFFF 8MB With Expansion Pak)
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constant RDRAM_BASE($A3F0) // $03F00000..$03F00027 RDRAM Base Register
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constant RDRAM_BASE($A3F0) // $03F00000..$03F00027 RDRAM Base Register
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constant RDRAM_DEVICE_TYPE($00) // $03F00000..$03F00003 RDRAM: Device Type Register
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constant RDRAM_DEVICE_TYPE($00) // $03F00000..$03F00003 RDRAM: Device Type Register
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constant RDRAM_DEVICE_ID($04) // $03F00004..$03F00007 RDRAM: Device ID Register
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constant RDRAM_DEVICE_ID($04) // $03F00004..$03F00007 RDRAM: Device ID Register
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constant RDRAM_MIN_INTERVAL($1C) // $03F0001C..$03F0001F RDRAM: Minimum Interval Register
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constant RDRAM_MIN_INTERVAL($1C) // $03F0001C..$03F0001F RDRAM: Minimum Interval Register
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constant RDRAM_ADDR_SELECT($20) // $03F00020..$03F00023 RDRAM: Address Select Register
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constant RDRAM_ADDR_SELECT($20) // $03F00020..$03F00023 RDRAM: Address Select Register
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constant RDRAM_DEVICE_MANUF($24) // $03F00024..$03F00027 RDRAM: Device Manufacturer Register
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constant RDRAM_DEVICE_MANUF($24) // $03F00024..$03F00027 RDRAM: Device Manufacturer Register
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constant SP_MEM_BASE($A400) // $04000000..$04000FFF SP MEM Base Register
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constant SP_DMEM($0000) // $04000000..$04000FFF SP: RSP DMEM (4096 Bytes)
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constant SP_IMEM($1000) // $04001000..$04001FFF SP: RSP IMEM (4096 Bytes)
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constant SP_BASE($A404) // $04040000..$0404001F SP Base Register
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constant SP_MEM_ADDR($00) // $04040000..$04040003 SP: Master, SP Memory Address Register
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constant SP_DRAM_ADDR($04) // $04040004..$04040007 SP: Slave, SP DRAM DMA Address Register
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constant SP_RD_LEN($08) // $04040008..$0404000B SP: Read DMA Length Register
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constant SP_WR_LEN($0C) // $0404000C..$0404000F SP: Write DMA Length Register
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constant SP_STATUS($10) // $04040010..$04040013 SP: Status Register
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constant SP_DMA_FULL($14) // $04040014..$04040017 SP: DMA Full Register
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constant SP_DMA_BUSY($18) // $04040018..$0404001B SP: DMA Busy Register
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constant SP_SEMAPHORE($1C) // $0404001C..$0404001F SP: Semaphore Register
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constant SP_PC_BASE($A408) // $04080000..$04080007 SP PC Base Register
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constant SP_PC($00) // $04080000..$04080003 SP: PC Register
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constant SP_IBIST_REG($04) // $04080004..$04080007 SP: IMEM BIST Register
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// SP_STATUS Read Flags:
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constant RSP_HLT($0001) // Halt
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constant RSP_BRK($0002) // Break
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constant RSP_BSY($0004) // DMA Busy
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constant RSP_FUL($0008) // DMA Full
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constant RSP_IOF($0010) // IO Full
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constant RSP_STP($0020) // Single Step
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constant RSP_IOB($0040) // Interrupt On Break
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constant RSP_SG0($0080) // Signal 0 Set
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constant RSP_SG1($0100) // Signal 1 Set
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constant RSP_SG2($0200) // Signal 2 Set
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constant RSP_SG3($0400) // Signal 3 Set
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constant RSP_SG4($0800) // Signal 4 Set
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constant RSP_SG5($1000) // Signal 5 Set
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constant RSP_SG6($2000) // Signal 6 Set
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constant RSP_SG7($4000) // Signal 7 Set
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// SP_STATUS Write Flags:
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constant CLR_HLT($00000001) // Clear Halt
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constant SET_HLT($00000002) // Set Halt
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constant CLR_BRK($00000004) // Clear Broke
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constant CLR_INT($00000008) // Clear Interrupt
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constant SET_INT($00000010) // Set Interrupt
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constant CLR_STP($00000020) // Clear Single Step
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constant SET_STP($00000040) // Set Single Step
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constant CLR_IOB($00000080) // Clear Interrupt On Break
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constant SET_IOB($00000100) // Set Interrupt On Break
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constant CLR_SG0($00000200) // Clear Signal 0
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constant SET_SG0($00000400) // Set Signal 0
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constant CLR_SG1($00000800) // Clear Signal 1
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constant SET_SG1($00001000) // Set Signal 1
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||||||
constant CLR_SG2($00002000) // Clear Signal 2
|
|
||||||
constant SET_SG2($00004000) // Set Signal 2
|
|
||||||
constant CLR_SG3($00008000) // Clear Signal 3
|
|
||||||
constant SET_SG3($00010000) // Set Signal 3
|
|
||||||
constant CLR_SG4($00020000) // Clear Signal 4
|
|
||||||
constant SET_SG4($00040000) // Set Signal 4
|
|
||||||
constant CLR_SG5($00080000) // Clear Signal 5
|
|
||||||
constant SET_SG5($00100000) // Set Signal 5
|
|
||||||
constant CLR_SG6($00200000) // Clear Signal 6
|
|
||||||
constant SET_SG6($00400000) // Set Signal 6
|
|
||||||
constant CLR_SG7($00800000) // Clear Signal 7
|
|
||||||
constant SET_SG7($01000000) // Set Signal 7
|
|
||||||
|
|
||||||
constant DPC_BASE($A410) // $04100000..$0410001F DP Command (DPC) Base Register
|
|
||||||
constant DPC_START($00) // $04100000..$04100003 DPC: CMD DMA Start Register
|
|
||||||
constant DPC_END($04) // $04100004..$04100007 DPC: CMD DMA End Register
|
|
||||||
constant DPC_CURRENT($08) // $04100008..$0410000B DPC: CMD DMA Current Register
|
|
||||||
constant DPC_STATUS($0C) // $0410000C..$0410000F DPC: CMD Status Register
|
|
||||||
constant DPC_CLOCK($10) // $04100010..$04100013 DPC: Clock Counter Register
|
|
||||||
constant DPC_BUFBUSY($14) // $04100014..$04100017 DPC: Buffer Busy Counter Register
|
|
||||||
constant DPC_PIPEBUSY($18) // $04100018..$0410001B DPC: Pipe Busy Counter Register
|
|
||||||
constant DPC_TMEM($1C) // $0410001C..$0410001F DPC: TMEM Load Counter Register
|
|
||||||
|
|
||||||
constant DPS_BASE($A420) // $04200000..$0420000F DP Span (DPS) Base Register
|
|
||||||
constant DPS_TBIST($00) // $04200000..$04200003 DPS: Tmem Bist Register
|
|
||||||
constant DPS_TEST_MODE($04) // $04200004..$04200007 DPS: Span Test Mode Register
|
|
||||||
constant DPS_BUFTEST_ADDR($08) // $04200008..$0420000B DPS: Span Buffer Test Address Register
|
|
||||||
constant DPS_BUFTEST_DATA($0C) // $0420000C..$0420000F DPS: Span Buffer Test Data Register
|
|
||||||
|
|
||||||
constant MI_BASE($A430) // $04300000..$0430000F MIPS Interface (MI) Base Register
|
|
||||||
constant MI_INIT_MODE($00) // $04300000..$04300003 MI: Init Mode Register
|
|
||||||
constant MI_VERSION($04) // $04300004..$04300007 MI: Version Register
|
|
||||||
constant MI_INTR($08) // $04300008..$0430000B MI: Interrupt Register
|
|
||||||
constant MI_INTR_MASK($0C) // $0430000C..$0430000F MI: Interrupt Mask Register
|
|
||||||
|
|
||||||
constant MI_INTR_SP($01)
|
|
||||||
constant MI_INTR_SI($02)
|
|
||||||
constant MI_INTR_AI($04)
|
|
||||||
constant MI_INTR_VI($08)
|
|
||||||
constant MI_INTR_PI($10)
|
|
||||||
constant MI_INTR_DP($20)
|
|
||||||
constant MI_INTR_ALL($3F)
|
|
||||||
|
|
||||||
// TODO: SET and CLR rather than just MASK
|
|
||||||
constant MI_INTR_MASK_SP($002)
|
|
||||||
constant MI_INTR_MASK_SI($008)
|
|
||||||
constant MI_INTR_MASK_AI($020)
|
|
||||||
constant MI_INTR_MASK_VI($080)
|
|
||||||
constant MI_INTR_MASK_PI($200)
|
|
||||||
constant MI_INTR_MASK_DP($800)
|
|
||||||
constant MI_INTR_MASK_ALL($AAA)
|
|
||||||
|
|
||||||
constant VI_BASE($A440) // $04400000..$04400037 Video Interface (VI) Base Register
|
|
||||||
constant VI_STATUS($00) // $04400000..$04400003 VI: Status/Control Register
|
|
||||||
constant VI_ORIGIN($04) // $04400004..$04400007 VI: Origin Register
|
|
||||||
constant VI_WIDTH($08) // $04400008..$0440000B VI: Width Register
|
|
||||||
constant VI_V_INTR($0C) // $0440000C..$0440000F VI: Vertical Interrupt Register
|
|
||||||
constant VI_V_CURRENT_LINE($10) // $04400010..$04400013 VI: Current Vertical Line Register
|
|
||||||
constant VI_TIMING($14) // $04400014..$04400017 VI: Video Timing Register
|
|
||||||
constant VI_V_SYNC($18) // $04400018..$0440001B VI: Vertical Sync Register
|
|
||||||
constant VI_H_SYNC($1C) // $0440001C..$0440001F VI: Horizontal Sync Register
|
|
||||||
constant VI_H_SYNC_LEAP($20) // $04400020..$04400023 VI: Horizontal Sync Leap Register
|
|
||||||
constant VI_H_VIDEO($24) // $04400024..$04400027 VI: Horizontal Video Register
|
|
||||||
constant VI_V_VIDEO($28) // $04400028..$0440002B VI: Vertical Video Register
|
|
||||||
constant VI_V_BURST($2C) // $0440002C..$0440002F VI: Vertical Burst Register
|
|
||||||
constant VI_X_SCALE($30) // $04400030..$04400033 VI: X-Scale Register
|
|
||||||
constant VI_Y_SCALE($34) // $04400034..$04400037 VI: Y-Scale Register
|
|
||||||
|
|
||||||
constant AI_BASE($A450) // $04500000..$04500017 Audio Interface (AI) Base Register
|
|
||||||
constant AI_DRAM_ADDR($00) // $04500000..$04500003 AI: DRAM Address Register
|
|
||||||
constant AI_LEN($04) // $04500004..$04500007 AI: Length Register
|
|
||||||
constant AI_CONTROL($08) // $04500008..$0450000B AI: Control Register
|
|
||||||
constant AI_STATUS($0C) // $0450000C..$0450000F AI: Status Register
|
|
||||||
constant AI_DACRATE($10) // $04500010..$04500013 AI: DAC Sample Period Register
|
|
||||||
constant AI_BITRATE($14) // $04500014..$04500017 AI: Bit Rate Register
|
|
||||||
|
|
||||||
constant PI_BASE($A460) // $04600000..$04600033 Peripheral Interface (PI) Base Register
|
|
||||||
constant PI_DRAM_ADDR($00) // $04600000..$04600003 PI: DRAM Address Register
|
|
||||||
constant PI_CART_ADDR($04) // $04600004..$04600007 PI: Pbus (Cartridge) Address Register
|
|
||||||
constant PI_RD_LEN($08) // $04600008..$0460000B PI: Read Length Register
|
|
||||||
constant PI_WR_LEN($0C) // $0460000C..$0460000F PI: Write length register
|
|
||||||
constant PI_STATUS($10) // $04600010..$04600013 PI: Status Register
|
|
||||||
constant PI_BSD_DOM1_LAT($14) // $04600014..$04600017 PI: Domain 1 Latency Register
|
|
||||||
constant PI_BSD_DOM1_PWD($18) // $04600018..$0460001B PI: Domain 1 Pulse Width Register
|
|
||||||
constant PI_BSD_DOM1_PGS($1C) // $0460001C..$0460001F PI: Domain 1 Page Size Register
|
|
||||||
constant PI_BSD_DOM1_RLS($20) // $04600020..$04600023 PI: Domain 1 Release Register
|
|
||||||
constant PI_BSD_DOM2_LAT($24) // $04600024..$04600027 PI: Domain 2 Latency Register
|
|
||||||
constant PI_BSD_DOM2_PWD($28) // $04600028..$0460002B PI: Domain 2 Pulse Width Register
|
|
||||||
constant PI_BSD_DOM2_PGS($2C) // $0460002C..$0460002F PI: Domain 2 Page Size Register
|
|
||||||
constant PI_BSD_DOM2_RLS($30) // $04600030..$04600033 PI: Domain 2 Release Register
|
|
||||||
|
|
||||||
constant RI_BASE($A470) // $04700000..$0470001F RDRAM Interface (RI) Base Register
|
|
||||||
constant RI_MODE($00) // $04700000..$04700003 RI: Mode Register
|
|
||||||
constant RI_CONFIG($04) // $04700004..$04700007 RI: Config Register
|
|
||||||
constant RI_CURRENT_LOAD($08) // $04700008..$0470000B RI: Current Load Register
|
|
||||||
constant RI_SELECT($0C) // $0470000C..$0470000F RI: Select Register
|
|
||||||
constant RI_REFRESH($10) // $04700010..$04700013 RI: Refresh Register
|
|
||||||
constant RI_LATENCY($14) // $04700014..$04700017 RI: Latency Register
|
|
||||||
constant RI_RERROR($18) // $04700018..$0470001B RI: Read Error Register
|
|
||||||
constant RI_WERROR($1C) // $0470001C..$0470001F RI: Write Error Register
|
|
||||||
|
|
||||||
constant SI_BASE($A480) // $04800000..$0480001B Serial Interface (SI) Base Register
|
|
||||||
constant SI_DRAM_ADDR($00) // $04800000..$04800003 SI: DRAM Address Register
|
|
||||||
constant SI_PIF_ADDR_RD64B($04) // $04800004..$04800007 SI: Address Read 64B Register
|
|
||||||
//*RESERVED*($08) // $04800008..$0480000B SI: Reserved Register
|
|
||||||
//*RESERVED*($0C) // $0480000C..$0480000F SI: Reserved Register
|
|
||||||
constant SI_PIF_ADDR_WR64B($10) // $04800010..$04800013 SI: Address Write 64B Register
|
|
||||||
//*RESERVED*($14) // $04800014..$04800017 SI: Reserved Register
|
|
||||||
constant SI_STATUS($18) // $04800018..$0480001B SI: Status Register
|
|
||||||
|
|
||||||
constant CART_DOM2_ADDR1($A500) // $05000000..$0507FFFF Cartridge Domain 2(Address 1) SRAM
|
|
||||||
constant CART_DOM1_ADDR1($A600) // $06000000..$07FFFFFF Cartridge Domain 1(Address 1) 64DD
|
|
||||||
constant CART_DOM2_ADDR2($A800) // $08000000..$0FFFFFFF Cartridge Domain 2(Address 2) SRAM
|
|
||||||
constant CART_DOM1_ADDR2($B000) // $10000000..$18000803 Cartridge Domain 1(Address 2) ROM
|
|
||||||
|
|
||||||
constant PIF_BASE($BFC0) // $1FC00000..$1FC007BF PIF Base Register
|
|
||||||
constant PIF_ROM($000) // $1FC00000..$1FC007BF PIF: Boot ROM
|
|
||||||
constant PIF_RAM($7C0) // $1FC007C0..$1FC007FF PIF: RAM (JoyChannel)
|
|
||||||
constant PIF_HWORD($7C4) // $1FC007C4..$1FC007C5 PIF: HWORD
|
|
||||||
constant PIF_XBYTE($7C6) // $1FC007C6 PIF: Analog X Byte
|
|
||||||
constant PIF_YBYTE($7C7) // $1FC007C7 PIF: Analog Y Byte
|
|
||||||
|
|
||||||
constant CART_DOM1_ADDR3($BFD0) // $1FD00000..$7FFFFFFF Cartridge Domain 1 (Address 3)
|
|
||||||
|
|
||||||
constant EXT_SYS_AD($8000) // $80000000..$FFFFFFFF External SysAD Device
|
|
||||||
|
|
||||||
constant VI_NTSC_CLOCK(48681812) // NTSC: Hz = 48.681812 MHz
|
|
||||||
constant VI_PAL_CLOCK(49656530) // PAL: Hz = 49.656530 MHz
|
|
||||||
constant VI_MPAL_CLOCK(48628316) // MPAL: Hz = 48.628316 MHz
|
|
||||||
|
|
||||||
macro align(size) { // Align Byte Amount
|
|
||||||
while (pc() % {size}) {
|
|
||||||
db 0
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
macro N64_INIT() {
|
|
||||||
// enables interrupts on SI and PI.
|
|
||||||
// must be done else N64 will stop responding.
|
|
||||||
lui a0,PIF_BASE // A0 = PIF Base Register ($BFC00000)
|
|
||||||
lli t0,8
|
|
||||||
sw t0,PIF_RAM+$3C(a0)
|
|
||||||
}
|
|
||||||
|
|
||||||
macro DMA(start, end, dest) { // DMA Data Copy Cart->DRAM: Start Cart Address, End Cart Address, Destination DRAM Address
|
|
||||||
lui a0,PI_BASE // A0 = PI Base Register ($A4600000)
|
|
||||||
-
|
|
||||||
lw t0,PI_STATUS(a0) // T0 = Word From PI Status Register ($A4600010)
|
|
||||||
andi t0,3 // AND PI Status With 3
|
|
||||||
bnez t0,- // IF TRUE DMA Is Busy
|
|
||||||
nop // Delay Slot
|
|
||||||
|
|
||||||
la t0,{dest}&$7FFFFF // T0 = Aligned DRAM Physical RAM Offset ($00000000..$007FFFFF 8MB)
|
|
||||||
sw t0,PI_DRAM_ADDR(a0) // Store RAM Offset To PI DRAM Address Register ($A4600000)
|
|
||||||
la t0,$10000000|({start}&$3FFFFFF) // T0 = Aligned Cart Physical ROM Offset ($10000000..$13FFFFFF 64MB)
|
|
||||||
sw t0,PI_CART_ADDR(a0) // Store ROM Offset To PI Cart Address Register ($A4600004)
|
|
||||||
la t0,({end}-{start})-1 // T0 = Length Of DMA Transfer In Bytes - 1
|
|
||||||
sw t0,PI_WR_LEN(a0) // Store DMA Length To PI Write Length Register ($A460000C)
|
|
||||||
}
|
|
||||||
|
|
|
||||||
7
inc/n64_ai.inc
Normal file
7
inc/n64_ai.inc
Normal file
|
|
@ -0,0 +1,7 @@
|
||||||
|
constant AI_BASE($A450) // $04500000..$04500017 Audio Interface (AI) Base Register
|
||||||
|
constant AI_DRAM_ADDR($00) // $04500000..$04500003 AI: DRAM Address Register
|
||||||
|
constant AI_LEN($04) // $04500004..$04500007 AI: Length Register
|
||||||
|
constant AI_CONTROL($08) // $04500008..$0450000B AI: Control Register
|
||||||
|
constant AI_STATUS($0C) // $0450000C..$0450000F AI: Status Register
|
||||||
|
constant AI_DACRATE($10) // $04500010..$04500013 AI: DAC Sample Period Register
|
||||||
|
constant AI_BITRATE($14) // $04500014..$04500017 AI: Bit Rate Register
|
||||||
95
inc/n64_cop0.inc
Normal file
95
inc/n64_cop0.inc
Normal file
|
|
@ -0,0 +1,95 @@
|
||||||
|
// Coprocessor 0 registers
|
||||||
|
constant CP0_Index(0)
|
||||||
|
constant CP0_Random(1)
|
||||||
|
constant CP0_EntryLo0(2)
|
||||||
|
constant CP0_EntryLo1(3)
|
||||||
|
constant CP0_Context(4)
|
||||||
|
constant CP0_PageMask(5)
|
||||||
|
constant CP0_Wired(6)
|
||||||
|
constant CP0_Reserved_1(7)
|
||||||
|
constant CP0_BadVAddr(8)
|
||||||
|
constant CP0_Count(9)
|
||||||
|
constant CP0_EntryHi(10)
|
||||||
|
constant CP0_Compare(11)
|
||||||
|
constant CP0_Status(12)
|
||||||
|
constant CP0_Cause(13)
|
||||||
|
constant CP0_EPC(14)
|
||||||
|
constant CP0_PRid(15)
|
||||||
|
constant CP0_Config(16)
|
||||||
|
constant CP0_LLAddr(17)
|
||||||
|
constant CP0_WatchLo(18)
|
||||||
|
constant CP0_WatchHi(19)
|
||||||
|
constant CP0_XContext(20)
|
||||||
|
constant CP0_Reserved_2(21)
|
||||||
|
constant CP0_Reserved_3(22)
|
||||||
|
constant CP0_Reserved_4(23)
|
||||||
|
constant CP0_Reserved_5(24)
|
||||||
|
constant CP0_Reserved_6(25)
|
||||||
|
constant CP0_PErr(26) // unused
|
||||||
|
constant CP0_CacheErr(27) // unused
|
||||||
|
constant CP0_TagLo(28)
|
||||||
|
constant CP0_TagHi(29) // reserved
|
||||||
|
constant CP0_ErrorPC(30)
|
||||||
|
constant CP0_Reserved_7(31)
|
||||||
|
|
||||||
|
constant CP0_STATUS_IE($0001) // Interrupt Enable
|
||||||
|
constant CP0_STATUS_EXL($0002) // Exception Level
|
||||||
|
constant CP0_STATUS_ERL($0004) // Error Level
|
||||||
|
constant CP0_STATUS_IM0($0100) // Interrupt Mask 0 (Software)
|
||||||
|
constant CP0_STATUS_IM1($0200) // Interrupt Mask 1 (Software)
|
||||||
|
constant CP0_STATUS_IM2($0400) // Interrupt Mask 2 (External)
|
||||||
|
constant CP0_STATUS_IM3($0800) // Interrupt Mask 3 (External)
|
||||||
|
constant CP0_STATUS_IM4($1000) // Interrupt Mask 4 (External)
|
||||||
|
constant CP0_STATUS_IM5($2000) // Interrupt Mask 5 (External)
|
||||||
|
constant CP0_STATUS_IM6($4000) // Interrupt Mask 6 (External)
|
||||||
|
constant CP0_STATUS_IM7($8000) // Interrupt Mask 7 (External)
|
||||||
|
constant CP0_STATUS_IM_ALL($FF01) // enable all interrupts
|
||||||
|
|
||||||
|
// note that these are all masks.
|
||||||
|
constant CP0_CAUSE_CODE($007C) // actually supposed to be called ExcCode
|
||||||
|
constant CP0_CAUSE_IP0($0100) // Interrupt Pending 0 (Software)
|
||||||
|
constant CP0_CAUSE_IP1($0200) // Interrupt Pending 1 (Software)
|
||||||
|
constant CP0_CAUSE_IP2($0400) // Interrupt Pending 2 (External)
|
||||||
|
constant CP0_CAUSE_IP3($0800) // Interrupt Pending 3 (External)
|
||||||
|
constant CP0_CAUSE_IP4($1000) // Interrupt Pending 4 (External)
|
||||||
|
constant CP0_CAUSE_IP5($2000) // Interrupt Pending 5 (External)
|
||||||
|
constant CP0_CAUSE_IP6($4000) // Interrupt Pending 6 (External)
|
||||||
|
constant CP0_CAUSE_IP7($8000) // Interrupt Pending 7 (External)
|
||||||
|
// upper halfword:
|
||||||
|
constant CP0_CAUSE_CE($30000000) // Coprocessor Error
|
||||||
|
constant CP0_CAUSE_BD($80000000) // Branch Delay (not an exception, just info)
|
||||||
|
|
||||||
|
// note that these constants are shifted left 2 into the Cause register,
|
||||||
|
// so you must unshift the value from the register before comparing them.
|
||||||
|
constant CP0_CODE_INT(0) // Interrupt
|
||||||
|
constant CP0_CODE_MOD(1) // TLB modification exception
|
||||||
|
constant CP0_CODE_TLBL(2) // TLB Exception (Load or instruction fetch)
|
||||||
|
constant CP0_CODE_TLBS(3) // TLB Exception (Store)
|
||||||
|
constant CP0_CODE_ADEL(4) // Address Error Exception (Load or instruction fetch)
|
||||||
|
constant CP0_CODE_ADES(5) // Address Error Exception (Store)
|
||||||
|
constant CP0_CODE_IBE(6) // Bus Error Exception (instruction fetch)
|
||||||
|
constant CP0_CODE_DBE(7) // Bus Error Exception (data reference: load or store)
|
||||||
|
constant CP0_CODE_SYS(8) // SysCall Exception
|
||||||
|
constant CP0_CODE_BP(9) // Breakpoint Exception
|
||||||
|
constant CP0_CODE_RI(10) // Reserved instruction Exception
|
||||||
|
constant CP0_CODE_CPU(11) // Coprocessor Unusable Exception
|
||||||
|
constant CP0_CODE_OV(12) // Arithmetic Overflow Exception
|
||||||
|
constant CP0_CODE_TR(13) // Trap Exception
|
||||||
|
constant CP0_CODE_RESERVED_14(14)
|
||||||
|
constant CP0_CODE_FPE(15) // Floating Point Exception
|
||||||
|
constant CP0_CODE_RESERVED_16(16)
|
||||||
|
constant CP0_CODE_RESERVED_17(17)
|
||||||
|
constant CP0_CODE_RESERVED_18(18)
|
||||||
|
constant CP0_CODE_RESERVED_19(19)
|
||||||
|
constant CP0_CODE_RESERVED_20(20)
|
||||||
|
constant CP0_CODE_RESERVED_21(21)
|
||||||
|
constant CP0_CODE_RESERVED_22(22)
|
||||||
|
constant CP0_CODE_WATCH(23) // Reference to WatchHi/WatchLo address
|
||||||
|
constant CP0_CODE_RESERVED_24(24)
|
||||||
|
constant CP0_CODE_RESERVED_25(25)
|
||||||
|
constant CP0_CODE_RESERVED_26(26)
|
||||||
|
constant CP0_CODE_RESERVED_27(27)
|
||||||
|
constant CP0_CODE_RESERVED_28(28)
|
||||||
|
constant CP0_CODE_RESERVED_29(29)
|
||||||
|
constant CP0_CODE_RESERVED_30(30)
|
||||||
|
constant CP0_CODE_RESERVED_31(31)
|
||||||
34
inc/n64_cop1.inc
Normal file
34
inc/n64_cop1.inc
Normal file
|
|
@ -0,0 +1,34 @@
|
||||||
|
// N64 MIPS 4300 CP1 Floating Point Unit (FPU) Registers (COP1)
|
||||||
|
constant f0(0)
|
||||||
|
constant f1(1)
|
||||||
|
constant f2(2)
|
||||||
|
constant f3(3)
|
||||||
|
constant f4(4)
|
||||||
|
constant f5(5)
|
||||||
|
constant f6(6)
|
||||||
|
constant f7(7)
|
||||||
|
constant f8(8)
|
||||||
|
constant f9(9)
|
||||||
|
constant f10(10)
|
||||||
|
constant f11(11)
|
||||||
|
constant f12(12)
|
||||||
|
constant f13(13)
|
||||||
|
constant f14(14)
|
||||||
|
constant f15(15)
|
||||||
|
constant f16(16)
|
||||||
|
constant f17(17)
|
||||||
|
constant f18(18)
|
||||||
|
constant f19(19)
|
||||||
|
constant f20(20)
|
||||||
|
constant f21(21)
|
||||||
|
constant f22(22)
|
||||||
|
constant f23(23)
|
||||||
|
constant f24(24)
|
||||||
|
constant f25(25)
|
||||||
|
constant f26(26)
|
||||||
|
constant f27(27)
|
||||||
|
constant f28(28)
|
||||||
|
constant f29(29)
|
||||||
|
constant f30(30)
|
||||||
|
constant f31(31)
|
||||||
|
|
||||||
67
inc/n64_cpu.inc
Normal file
67
inc/n64_cpu.inc
Normal file
|
|
@ -0,0 +1,67 @@
|
||||||
|
// N64 MIPS 4300 CPU Registers
|
||||||
|
constant r0(0)
|
||||||
|
constant r1(1)
|
||||||
|
constant r2(2)
|
||||||
|
constant r3(3)
|
||||||
|
constant r4(4)
|
||||||
|
constant r5(5)
|
||||||
|
constant r6(6)
|
||||||
|
constant r7(7)
|
||||||
|
constant r8(8)
|
||||||
|
constant r9(9)
|
||||||
|
constant r10(10)
|
||||||
|
constant r11(11)
|
||||||
|
constant r12(12)
|
||||||
|
constant r13(13)
|
||||||
|
constant r14(14)
|
||||||
|
constant r15(15)
|
||||||
|
constant r16(16)
|
||||||
|
constant r17(17)
|
||||||
|
constant r18(18)
|
||||||
|
constant r19(19)
|
||||||
|
constant r20(20)
|
||||||
|
constant r21(21)
|
||||||
|
constant r22(22)
|
||||||
|
constant r23(23)
|
||||||
|
constant r24(24)
|
||||||
|
constant r25(25)
|
||||||
|
constant r26(26)
|
||||||
|
constant r27(27)
|
||||||
|
constant r28(28)
|
||||||
|
constant r29(29)
|
||||||
|
constant r30(30)
|
||||||
|
constant r31(31)
|
||||||
|
|
||||||
|
constant at(1)
|
||||||
|
constant v0(2)
|
||||||
|
constant v1(3)
|
||||||
|
constant a0(4)
|
||||||
|
constant a1(5)
|
||||||
|
constant a2(6)
|
||||||
|
constant a3(7)
|
||||||
|
constant t0(8)
|
||||||
|
constant t1(9)
|
||||||
|
constant t2(10)
|
||||||
|
constant t3(11)
|
||||||
|
constant t4(12)
|
||||||
|
constant t5(13)
|
||||||
|
constant t6(14)
|
||||||
|
constant t7(15)
|
||||||
|
constant s0(16)
|
||||||
|
constant s1(17)
|
||||||
|
constant s2(18)
|
||||||
|
constant s3(19)
|
||||||
|
constant s4(20)
|
||||||
|
constant s5(21)
|
||||||
|
constant s6(22)
|
||||||
|
constant s7(23)
|
||||||
|
constant t8(24)
|
||||||
|
constant t9(25)
|
||||||
|
constant k0(26)
|
||||||
|
constant k1(27)
|
||||||
|
constant gp(28)
|
||||||
|
constant sp(29)
|
||||||
|
constant fp(30)
|
||||||
|
constant ra(31)
|
||||||
|
|
||||||
|
constant s8(30) // alias of fp
|
||||||
16
inc/n64_dp.inc
Normal file
16
inc/n64_dp.inc
Normal file
|
|
@ -0,0 +1,16 @@
|
||||||
|
constant DPC_BASE($A410) // $04100000..$0410001F DP Command (DPC) Base Register
|
||||||
|
constant DPC_START($00) // $04100000..$04100003 DPC: CMD DMA Start Register
|
||||||
|
constant DPC_END($04) // $04100004..$04100007 DPC: CMD DMA End Register
|
||||||
|
constant DPC_CURRENT($08) // $04100008..$0410000B DPC: CMD DMA Current Register
|
||||||
|
constant DPC_STATUS($0C) // $0410000C..$0410000F DPC: CMD Status Register
|
||||||
|
constant DPC_CLOCK($10) // $04100010..$04100013 DPC: Clock Counter Register
|
||||||
|
constant DPC_BUFBUSY($14) // $04100014..$04100017 DPC: Buffer Busy Counter Register
|
||||||
|
constant DPC_PIPEBUSY($18) // $04100018..$0410001B DPC: Pipe Busy Counter Register
|
||||||
|
constant DPC_TMEM($1C) // $0410001C..$0410001F DPC: TMEM Load Counter Register
|
||||||
|
|
||||||
|
constant DPS_BASE($A420) // $04200000..$0420000F DP Span (DPS) Base Register
|
||||||
|
constant DPS_TBIST($00) // $04200000..$04200003 DPS: Tmem Bist Register
|
||||||
|
constant DPS_TEST_MODE($04) // $04200004..$04200007 DPS: Span Test Mode Register
|
||||||
|
constant DPS_BUFTEST_ADDR($08) // $04200008..$0420000B DPS: Span Buffer Test Address Register
|
||||||
|
constant DPS_BUFTEST_DATA($0C) // $0420000C..$0420000F DPS: Span Buffer Test Data Register
|
||||||
|
|
||||||
111
inc/n64_gfx.inc
111
inc/n64_gfx.inc
|
|
@ -1,116 +1,5 @@
|
||||||
// via krom
|
// via krom
|
||||||
|
|
||||||
//==============
|
|
||||||
// N64 Graphics
|
|
||||||
//==============
|
|
||||||
constant BPP0($0000) // VI Status/Control: Color Depth Blank (No Data Or Sync) (Bit 0..1)
|
|
||||||
//*RESERVED*($0001) // VI Status/Control: Color Depth Reserved (Bit 0..1)
|
|
||||||
constant BPP16($0002) // VI Status/Control: Color Depth 16BPP R5/G5/B5/A1 (Bit 0..1)
|
|
||||||
constant BPP32($0003) // VI Status/Control: Color Depth 32BPP R8/G8/B8/A8 (Bit 0..1)
|
|
||||||
constant GAMMA_DITHER_EN($00004) // VI Status/Control: Gamma Dither Enable (Requires: Gamma Enable) (Bit 2)
|
|
||||||
constant GAMMA_EN($00008) // VI Status/Control: Gamma Enable (Gamma Boost For YUV Images) (Bit 3)
|
|
||||||
constant DIVOT_EN($00010) // VI Status/Control: Divot Enable (Used With Anti-alias) (Bit 4)
|
|
||||||
constant VBUS_CLK_EN($00020) // VI Status/Control: Video Bus Clock Enable (Bit 5)
|
|
||||||
constant INTERLACE($00040) // VI Status/Control: Interlace/Serrate (Used With Interlaced Display) (Bit 6)
|
|
||||||
constant TST_MODE($00080) // VI Status/Control: Test Mode (Bit 7)
|
|
||||||
constant AA_MODE_0($00000) // VI Status/Control: AA Mode 0 = Anti-alias & Resample (Always Fetch Extra Lines) (Bit 8..9)
|
|
||||||
constant AA_MODE_1($00100) // VI Status/Control: AA Mode 1 = Anti-alias & Resample (Fetch Extra Lines When Needed) (Bit 8..9)
|
|
||||||
constant AA_MODE_2($00200) // VI Status/Control: AA Mode 2 = Resample Only (Bit 8..9)
|
|
||||||
constant AA_MODE_3($00300) // VI Status/Control: AA Mode 3 = Replicate Pixels & No Interpolation (Bit 8..9)
|
|
||||||
constant DIAG_0($00400) // VI Status/Control: Diagnotic 0 (Bit 10..11)
|
|
||||||
constant DIAG_1($00800) // VI Status/Control: Diagnotic 1 (Bit 10..11)
|
|
||||||
constant PIXEL_ADV_0($00000) // VI Status/Control: Pixel Advance 0 (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_1($01000) // VI Status/Control: Pixel Advance 1 (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_2($02000) // VI Status/Control: Pixel Advance 2 (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_3($03000) // VI Status/Control: Pixel Advance 3 (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_4($04000) // VI Status/Control: Pixel Advance 4 (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_5($05000) // VI Status/Control: Pixel Advance 5 (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_6($06000) // VI Status/Control: Pixel Advance 6 (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_7($07000) // VI Status/Control: Pixel Advance 7 (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_8($08000) // VI Status/Control: Pixel Advance 8 (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_9($09000) // VI Status/Control: Pixel Advance 9 (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_A($0A000) // VI Status/Control: Pixel Advance A (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_B($0B000) // VI Status/Control: Pixel Advance B (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_C($0C000) // VI Status/Control: Pixel Advance C (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_D($0D000) // VI Status/Control: Pixel Advance D (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_E($0E000) // VI Status/Control: Pixel Advance E (Bit 12..15)
|
|
||||||
constant PIXEL_ADV_F($0F000) // VI Status/Control: Pixel Advance F (Bit 12..15)
|
|
||||||
constant DITHER_FILTER_EN($10000) // VI Status/Control: Dither Filter Enable (Used With 16BPP Display) (Bit 16)
|
|
||||||
|
|
||||||
macro ScreenNTSC(width,height, status, origin) {
|
|
||||||
lui a0,VI_BASE // A0 = VI Base Register ($A4400000)
|
|
||||||
li t0,{status} // T0 = Status/Control
|
|
||||||
sw t0,VI_STATUS(a0) // Store Status/Control To VI Status Register ($A4400000)
|
|
||||||
la t0,{origin} // T0 = Origin (Frame Buffer Origin In Bytes)
|
|
||||||
sw t0,VI_ORIGIN(a0) // Store Origin To VI Origin Register ($A4400004)
|
|
||||||
lli t0,{width} // T0 = Width (Frame Buffer Line Width In Pixels)
|
|
||||||
sw t0,VI_WIDTH(a0) // Store Width To VI Width Register ($A4400008)
|
|
||||||
lli t0,$200 // T0 = Vertical Interrupt (Interrupt When Current Half-Line $200)
|
|
||||||
sw t0,VI_V_INTR(a0) // Store Vertical Interrupt To VI Interrupt Register ($A440000C)
|
|
||||||
lli t0,0 // T0 = Current Vertical Line (Current Half-Line, Sampled Once Per Line = 0)
|
|
||||||
sw t0,VI_V_CURRENT_LINE(a0) // Store Current Vertical Line To VI Current Register ($A4400010)
|
|
||||||
li t0,$3E52239 // T0 = Video Timing (Start Of Color Burst In Pixels from H-Sync = 3, Vertical Sync Width In Half Lines = 229, Color Burst Width In Pixels = 34, Horizontal Sync Width In Pixels = 57)
|
|
||||||
sw t0,VI_TIMING(a0) // Store Video Timing To VI Burst Register ($A4400014)
|
|
||||||
lli t0,$20D // T0 = Vertical Sync (Number Of Half-Lines Per Field = 525)
|
|
||||||
sw t0,VI_V_SYNC(a0) // Store Vertical Sync To VI V Sync Register ($A4400018)
|
|
||||||
lli t0,$C15 // T0 = Horizontal Sync (5-bit Leap Pattern Used For PAL only = 0, Total Duration Of A Line In 1/4 Pixel = 3093)
|
|
||||||
sw t0,VI_H_SYNC(a0) // Store Horizontal Sync To VI H Sync Register ($A440001C)
|
|
||||||
li t0,$C150C15 // T0 = Horizontal Sync Leap (Identical To H Sync = 3093, Identical To H Sync = 3093)
|
|
||||||
sw t0,VI_H_SYNC_LEAP(a0) // Store Horizontal Sync Leap To VI Leap Register ($A4400020)
|
|
||||||
li t0,$6C02EC // T0 = Horizontal Video (Start Of Active Video In Screen Pixels = 108, End Of Active Video In Screen Pixels = 748)
|
|
||||||
sw t0,VI_H_VIDEO(a0) // Store Horizontal Video To VI H Start Register ($A4400024)
|
|
||||||
li t0,$2501FF // T0 = Vertical Video (Start Of Active Video In Screen Half-Lines = 37, End Of Active Video In Screen Half-Lines = 511)
|
|
||||||
sw t0,VI_V_VIDEO(a0) // Store Vertical Video To VI V Start Register ($A4400028)
|
|
||||||
li t0,$E0204 // T0 = Vertical Burst (Start Of Color Burst Enable In Half-Lines = 14, End Of Color Burst Enable In Half-Lines = 516)
|
|
||||||
sw t0,VI_V_BURST(a0) // Store Vertical Burst To VI V Burst Register ($A440002C)
|
|
||||||
lli t0,($100*({width}/160)) // T0 = X-Scale (Horizontal Subpixel Offset In 2.10 Format = 0, 1/Horizontal Scale Up Factor In 2.10 Format)
|
|
||||||
sw t0,VI_X_SCALE(a0) // Store X-Scale To VI X Scale Register ($A4400030)
|
|
||||||
lli t0,($100*({height}/60)) // T0 = Y-Scale (Vertical Subpixel Offset In 2.10 Format = 0, 1/Vertical Scale Up Factor In 2.10 Format)
|
|
||||||
sw t0,VI_Y_SCALE(a0) // Store Y-Scale To VI Y Scale Register ($A4400034)
|
|
||||||
}
|
|
||||||
|
|
||||||
macro ScreenPAL(width,height, status, origin) {
|
|
||||||
lui a0,VI_BASE // A0 = VI Base Register ($A4400000)
|
|
||||||
la t0,{origin} // T0 = Origin (Frame Buffer Origin In Bytes)
|
|
||||||
sw t0,VI_ORIGIN(a0) // Store Origin To VI Origin Register ($A4400004)
|
|
||||||
lli t0,{width} // T0 = Width (Frame Buffer Line Width In Pixels)
|
|
||||||
sw t0,VI_WIDTH(a0) // Store Width To VI Width Register ($A4400008)
|
|
||||||
lli t0,$200 // T0 = Vertical Interrupt (Interrupt When Current Half-Line $200)
|
|
||||||
//lli t0,2
|
|
||||||
sw t0,VI_V_INTR(a0) // Store Vertical Interrupt To VI Interrupt Register ($A440000C)
|
|
||||||
lli t0,0 // T0 = Current Vertical Line (Current Half-Line, Sampled Once Per Line = 0)
|
|
||||||
sw t0,VI_V_CURRENT_LINE(a0) // Store Current Vertical Line To VI Current Register ($A4400010)
|
|
||||||
li t0,$404233A // T0 = Video Timing (Start Of Color Burst In Pixels from H-Sync = 4, Vertical Sync Width In Half Lines = 04, Color Burst Width In Pixels = 35, Horizontal Sync Width In Pixels = 58)
|
|
||||||
sw t0,VI_TIMING(a0) // Store Video Timing To VI Burst Register ($A4400014)
|
|
||||||
lli t0,$271 // T0 = Vertical Sync (Number Of Half-Lines Per Field = 625)
|
|
||||||
sw t0,VI_V_SYNC(a0) // Store Vertical Sync To VI V Sync Register ($A4400018)
|
|
||||||
li t0,$150C69 // T0 = Horizontal Sync (5-bit Leap Pattern Used For PAL only = 21: %10101, Total Duration Of A Line In 1/4 Pixel = 3177)
|
|
||||||
sw t0,VI_H_SYNC(a0) // Store Horizontal Sync To VI H Sync Register ($A440001C)
|
|
||||||
li t0,$C6F0C6E // T0 = Horizontal Sync Leap (Identical To H Sync = 3183, Identical To H Sync = 3182)
|
|
||||||
sw t0,VI_H_SYNC_LEAP(a0) // Store Horizontal Sync Leap To VI Leap Register ($A4400020)
|
|
||||||
li t0,$800300 // T0 = Horizontal Video (Start Of Active Video In Screen Pixels = 128, End Of Active Video In Screen Pixels = 768)
|
|
||||||
sw t0,VI_H_VIDEO(a0) // Store Horizontal Video To VI H Start Register ($A4400024)
|
|
||||||
li t0,$5F0239 // T0 = Vertical Video (Start Of Active Video In Screen Half-Lines = 95, End Of Active Video In Screen Half-Lines = 569)
|
|
||||||
sw t0,VI_V_VIDEO(a0) // Store Vertical Video To VI V Start Register ($A4400028)
|
|
||||||
li t0,$9026B // T0 = Vertical Burst (Start Of Color Burst Enable In Half-Lines = 9, End Of Color Burst Enable In Half-Lines = 619)
|
|
||||||
sw t0,VI_V_BURST(a0) // Store Vertical Burst To VI V Burst Register ($A440002C)
|
|
||||||
lli t0,($100*({width}/160)) // T0 = X-Scale (Horizontal Subpixel Offset In 2.10 Format = 0, 1/Horizontal Scale Up Factor In 2.10 Format)
|
|
||||||
sw t0,VI_X_SCALE(a0) // Store X-Scale To VI X Scale Register ($A4400030)
|
|
||||||
lli t0,($100*({height}/60)) // T0 = Y-Scale (Vertical Subpixel Offset In 2.10 Format = 0, 1/Vertical Scale Up Factor In 2.10 Format)
|
|
||||||
sw t0,VI_Y_SCALE(a0) // Store Y-Scale To VI Y Scale Register ($A4400034)
|
|
||||||
li t0,{status} // T0 = Status/Control
|
|
||||||
sw t0,VI_STATUS(a0) // Store Status/Control To VI Status Register ($A4400000)
|
|
||||||
}
|
|
||||||
|
|
||||||
macro WaitScanline(scanline) { // Wait For RDP To Reach Scanline
|
|
||||||
lui a0,VI_BASE // A0 = VI Base Register ($A4400000)
|
|
||||||
lli t0,{scanline} // T0 = Scan Line
|
|
||||||
-
|
|
||||||
lw t1,VI_V_CURRENT_LINE(a0) // T1 = Current Scan Line
|
|
||||||
bne t1,t0,- // IF (Current Scan Line != Scan Line) Wait
|
|
||||||
nop // ELSE Continue (Delay Slot)
|
|
||||||
}
|
|
||||||
|
|
||||||
// RDP Commands
|
// RDP Commands
|
||||||
macro DPC(start,end) { // Run DPC Command Buffer: Start Address, End Address
|
macro DPC(start,end) { // Run DPC Command Buffer: Start Address, End Address
|
||||||
lui a0,DPC_BASE // A0 = Reality Display Processer Control Interface Base Register ($A4100000)
|
lui a0,DPC_BASE // A0 = Reality Display Processer Control Interface Base Register ($A4100000)
|
||||||
|
|
|
||||||
11
inc/n64_map.inc
Normal file
11
inc/n64_map.inc
Normal file
|
|
@ -0,0 +1,11 @@
|
||||||
|
constant EXT_SYS_AD($8000) // $80000000..$FFFFFFFF External SysAD Device
|
||||||
|
constant RDRAM($A000) // $00000000..$003FFFFF RDRAM Memory 4MB ($00000000..$007FFFFF 8MB With Expansion Pak)
|
||||||
|
|
||||||
|
constant UNCACHED(0xA0000000)
|
||||||
|
constant ADDR_MASK(0x1FFFFFFF)
|
||||||
|
|
||||||
|
constant CART_DOM2_ADDR1($A500) // $05000000..$0507FFFF Cartridge Domain 2 (Address 1) SRAM
|
||||||
|
constant CART_DOM1_ADDR1($A600) // $06000000..$07FFFFFF Cartridge Domain 1 (Address 1) 64DD
|
||||||
|
constant CART_DOM2_ADDR2($A800) // $08000000..$0FFFFFFF Cartridge Domain 2 (Address 2) SRAM
|
||||||
|
constant CART_DOM1_ADDR2($B000) // $10000000..$18000803 Cartridge Domain 1 (Address 2) ROM
|
||||||
|
constant CART_DOM1_ADDR3($BFD0) // $1FD00000..$7FFFFFFF Cartridge Domain 1 (Address 3)
|
||||||
22
inc/n64_mi.inc
Normal file
22
inc/n64_mi.inc
Normal file
|
|
@ -0,0 +1,22 @@
|
||||||
|
constant MI_BASE($A430) // $04300000..$0430000F MIPS Interface (MI) Base Register
|
||||||
|
constant MI_INIT_MODE($00) // $04300000..$04300003 MI: Init Mode Register
|
||||||
|
constant MI_VERSION($04) // $04300004..$04300007 MI: Version Register
|
||||||
|
constant MI_INTR($08) // $04300008..$0430000B MI: Interrupt Register
|
||||||
|
constant MI_INTR_MASK($0C) // $0430000C..$0430000F MI: Interrupt Mask Register
|
||||||
|
|
||||||
|
constant MI_INTR_SP($01)
|
||||||
|
constant MI_INTR_SI($02)
|
||||||
|
constant MI_INTR_AI($04)
|
||||||
|
constant MI_INTR_VI($08)
|
||||||
|
constant MI_INTR_PI($10)
|
||||||
|
constant MI_INTR_DP($20)
|
||||||
|
constant MI_INTR_ALL($3F)
|
||||||
|
|
||||||
|
// TODO: SET and CLR rather than just MASK
|
||||||
|
constant MI_INTR_MASK_SP($002)
|
||||||
|
constant MI_INTR_MASK_SI($008)
|
||||||
|
constant MI_INTR_MASK_AI($020)
|
||||||
|
constant MI_INTR_MASK_VI($080)
|
||||||
|
constant MI_INTR_MASK_PI($200)
|
||||||
|
constant MI_INTR_MASK_DP($800)
|
||||||
|
constant MI_INTR_MASK_ALL($AAA)
|
||||||
23
inc/n64_pi.inc
Normal file
23
inc/n64_pi.inc
Normal file
|
|
@ -0,0 +1,23 @@
|
||||||
|
constant PI_BASE($A460) // $04600000..$04600033 Peripheral Interface (PI) Base Register
|
||||||
|
constant PI_DRAM_ADDR($00) // $04600000..$04600003 PI: DRAM Address Register
|
||||||
|
constant PI_CART_ADDR($04) // $04600004..$04600007 PI: Pbus (Cartridge) Address Register
|
||||||
|
constant PI_RD_LEN($08) // $04600008..$0460000B PI: Read Length Register
|
||||||
|
constant PI_WR_LEN($0C) // $0460000C..$0460000F PI: Write length register
|
||||||
|
constant PI_STATUS($10) // $04600010..$04600013 PI: Status Register
|
||||||
|
constant PI_BSD_DOM1_LAT($14) // $04600014..$04600017 PI: Domain 1 Latency Register
|
||||||
|
constant PI_BSD_DOM1_PWD($18) // $04600018..$0460001B PI: Domain 1 Pulse Width Register
|
||||||
|
constant PI_BSD_DOM1_PGS($1C) // $0460001C..$0460001F PI: Domain 1 Page Size Register
|
||||||
|
constant PI_BSD_DOM1_RLS($20) // $04600020..$04600023 PI: Domain 1 Release Register
|
||||||
|
constant PI_BSD_DOM2_LAT($24) // $04600024..$04600027 PI: Domain 2 Latency Register
|
||||||
|
constant PI_BSD_DOM2_PWD($28) // $04600028..$0460002B PI: Domain 2 Pulse Width Register
|
||||||
|
constant PI_BSD_DOM2_PGS($2C) // $0460002C..$0460002F PI: Domain 2 Page Size Register
|
||||||
|
constant PI_BSD_DOM2_RLS($30) // $04600030..$04600033 PI: Domain 2 Release Register
|
||||||
|
|
||||||
|
macro PI_WAIT() {
|
||||||
|
lui t5, PI_BASE
|
||||||
|
-
|
||||||
|
lw t0, PI_STATUS(t5)
|
||||||
|
andi t0, t0, 3
|
||||||
|
bnez t0,-
|
||||||
|
nop
|
||||||
|
}
|
||||||
6
inc/n64_pif.inc
Normal file
6
inc/n64_pif.inc
Normal file
|
|
@ -0,0 +1,6 @@
|
||||||
|
constant PIF_BASE($BFC0) // $1FC00000..$1FC007BF PIF Base Register
|
||||||
|
constant PIF_ROM($000) // $1FC00000..$1FC007BF PIF: Boot ROM
|
||||||
|
constant PIF_RAM($7C0) // $1FC007C0..$1FC007FF PIF: RAM (JoyChannel)
|
||||||
|
constant PIF_HWORD($7C4) // $1FC007C4..$1FC007C5 PIF: HWORD
|
||||||
|
constant PIF_XBYTE($7C6) // $1FC007C6 PIF: Analog X Byte
|
||||||
|
constant PIF_YBYTE($7C7) // $1FC007C7 PIF: Analog Y Byte
|
||||||
9
inc/n64_ri.inc
Normal file
9
inc/n64_ri.inc
Normal file
|
|
@ -0,0 +1,9 @@
|
||||||
|
constant RI_BASE($A470) // $04700000..$0470001F RDRAM Interface (RI) Base Register
|
||||||
|
constant RI_MODE($00) // $04700000..$04700003 RI: Mode Register
|
||||||
|
constant RI_CONFIG($04) // $04700004..$04700007 RI: Config Register
|
||||||
|
constant RI_CURRENT_LOAD($08) // $04700008..$0470000B RI: Current Load Register
|
||||||
|
constant RI_SELECT($0C) // $0470000C..$0470000F RI: Select Register
|
||||||
|
constant RI_REFRESH($10) // $04700010..$04700013 RI: Refresh Register
|
||||||
|
constant RI_LATENCY($14) // $04700014..$04700017 RI: Latency Register
|
||||||
|
constant RI_RERROR($18) // $04700018..$0470001B RI: Read Error Register
|
||||||
|
constant RI_WERROR($1C) // $0470001C..$0470001F RI: Write Error Register
|
||||||
8
inc/n64_si.inc
Normal file
8
inc/n64_si.inc
Normal file
|
|
@ -0,0 +1,8 @@
|
||||||
|
constant SI_BASE($A480) // $04800000..$0480001B Serial Interface (SI) Base Register
|
||||||
|
constant SI_DRAM_ADDR($00) // $04800000..$04800003 SI: DRAM Address Register
|
||||||
|
constant SI_PIF_ADDR_RD64B($04) // $04800004..$04800007 SI: Address Read 64B Register
|
||||||
|
//*RESERVED*($08) // $04800008..$0480000B SI: Reserved Register
|
||||||
|
//*RESERVED*($0C) // $0480000C..$0480000F SI: Reserved Register
|
||||||
|
constant SI_PIF_ADDR_WR64B($10) // $04800010..$04800013 SI: Address Write 64B Register
|
||||||
|
//*RESERVED*($14) // $04800014..$04800017 SI: Reserved Register
|
||||||
|
constant SI_STATUS($18) // $04800018..$0480001B SI: Status Register
|
||||||
83
inc/n64_sp.inc
Normal file
83
inc/n64_sp.inc
Normal file
|
|
@ -0,0 +1,83 @@
|
||||||
|
constant SP_MEM_BASE($A400) // $04000000..$04000FFF SP MEM Base Register
|
||||||
|
constant SP_DMEM($0000) // $04000000..$04000FFF SP: RSP DMEM (4096 Bytes)
|
||||||
|
constant SP_IMEM($1000) // $04001000..$04001FFF SP: RSP IMEM (4096 Bytes)
|
||||||
|
|
||||||
|
constant SP_BASE($A404) // $04040000..$0404001F SP Base Register
|
||||||
|
constant SP_MEM_ADDR($00) // $04040000..$04040003 SP: Master, SP Memory Address Register
|
||||||
|
constant SP_DRAM_ADDR($04) // $04040004..$04040007 SP: Slave, SP DRAM DMA Address Register
|
||||||
|
constant SP_RD_LEN($08) // $04040008..$0404000B SP: Read DMA Length Register
|
||||||
|
constant SP_WR_LEN($0C) // $0404000C..$0404000F SP: Write DMA Length Register
|
||||||
|
constant SP_STATUS($10) // $04040010..$04040013 SP: Status Register
|
||||||
|
constant SP_DMA_FULL($14) // $04040014..$04040017 SP: DMA Full Register
|
||||||
|
constant SP_DMA_BUSY($18) // $04040018..$0404001B SP: DMA Busy Register
|
||||||
|
constant SP_SEMAPHORE($1C) // $0404001C..$0404001F SP: Semaphore Register
|
||||||
|
|
||||||
|
constant SP_PC_BASE($A408) // $04080000..$04080007 SP PC Base Register
|
||||||
|
constant SP_PC($00) // $04080000..$04080003 SP: PC Register
|
||||||
|
constant SP_IBIST_REG($04) // $04080004..$04080007 SP: IMEM BIST Register
|
||||||
|
|
||||||
|
// SP_STATUS Read Flags:
|
||||||
|
constant RSP_HLT($0001) // Halt
|
||||||
|
constant RSP_BRK($0002) // Break
|
||||||
|
constant RSP_BSY($0004) // DMA Busy
|
||||||
|
constant RSP_FUL($0008) // DMA Full
|
||||||
|
constant RSP_IOF($0010) // IO Full
|
||||||
|
constant RSP_STP($0020) // Single Step
|
||||||
|
constant RSP_IOB($0040) // Interrupt On Break
|
||||||
|
constant RSP_SG0($0080) // Signal 0 Set
|
||||||
|
constant RSP_SG1($0100) // Signal 1 Set
|
||||||
|
constant RSP_SG2($0200) // Signal 2 Set
|
||||||
|
constant RSP_SG3($0400) // Signal 3 Set
|
||||||
|
constant RSP_SG4($0800) // Signal 4 Set
|
||||||
|
constant RSP_SG5($1000) // Signal 5 Set
|
||||||
|
constant RSP_SG6($2000) // Signal 6 Set
|
||||||
|
constant RSP_SG7($4000) // Signal 7 Set
|
||||||
|
|
||||||
|
// SP_STATUS Write Flags:
|
||||||
|
constant CLR_HLT($00000001) // Clear Halt
|
||||||
|
constant SET_HLT($00000002) // Set Halt
|
||||||
|
constant CLR_BRK($00000004) // Clear Broke
|
||||||
|
constant CLR_INT($00000008) // Clear Interrupt
|
||||||
|
constant SET_INT($00000010) // Set Interrupt
|
||||||
|
constant CLR_STP($00000020) // Clear Single Step
|
||||||
|
constant SET_STP($00000040) // Set Single Step
|
||||||
|
constant CLR_IOB($00000080) // Clear Interrupt On Break
|
||||||
|
constant SET_IOB($00000100) // Set Interrupt On Break
|
||||||
|
constant CLR_SG0($00000200) // Clear Signal 0
|
||||||
|
constant SET_SG0($00000400) // Set Signal 0
|
||||||
|
constant CLR_SG1($00000800) // Clear Signal 1
|
||||||
|
constant SET_SG1($00001000) // Set Signal 1
|
||||||
|
constant CLR_SG2($00002000) // Clear Signal 2
|
||||||
|
constant SET_SG2($00004000) // Set Signal 2
|
||||||
|
constant CLR_SG3($00008000) // Clear Signal 3
|
||||||
|
constant SET_SG3($00010000) // Set Signal 3
|
||||||
|
constant CLR_SG4($00020000) // Clear Signal 4
|
||||||
|
constant SET_SG4($00040000) // Set Signal 4
|
||||||
|
constant CLR_SG5($00080000) // Clear Signal 5
|
||||||
|
constant SET_SG5($00100000) // Set Signal 5
|
||||||
|
constant CLR_SG6($00200000) // Clear Signal 6
|
||||||
|
constant SET_SG6($00400000) // Set Signal 6
|
||||||
|
constant CLR_SG7($00800000) // Clear Signal 7
|
||||||
|
constant SET_SG7($01000000) // Set Signal 7
|
||||||
|
|
||||||
|
macro SP_DMA_WAIT() { // from CPU
|
||||||
|
lui t5, SP_BASE
|
||||||
|
-
|
||||||
|
lw t0, SP_DMA_FULL(t5)
|
||||||
|
bnez t0,-
|
||||||
|
nop
|
||||||
|
-
|
||||||
|
lw t0, SP_DMA_BUSY(t5)
|
||||||
|
bnez t0,-
|
||||||
|
nop
|
||||||
|
}
|
||||||
|
|
||||||
|
macro SP_BUSY_WAIT() {
|
||||||
|
lui a0, SP_BASE
|
||||||
|
-
|
||||||
|
lw t0, SP_STATUS(a0)
|
||||||
|
andi t0, 0x1C
|
||||||
|
sltu t0, r0, t0 // TODO: rewrite this
|
||||||
|
bnez t0,-
|
||||||
|
nop
|
||||||
|
}
|
||||||
15
inc/n64_util.inc
Normal file
15
inc/n64_util.inc
Normal file
|
|
@ -0,0 +1,15 @@
|
||||||
|
macro EnableInt() {
|
||||||
|
lli t0, 0xAAA
|
||||||
|
lli t1, 0xFF01
|
||||||
|
lui a0, MI_BASE
|
||||||
|
sw t0, MI_INTR_MASK(a0)
|
||||||
|
mtc0 t1, CP0_Status
|
||||||
|
}
|
||||||
|
|
||||||
|
macro DisableInt() {
|
||||||
|
lli t0, 0x555
|
||||||
|
lli t1, 0x0001
|
||||||
|
lui a0, MI_BASE
|
||||||
|
sw t0, MI_INTR_MASK(a0)
|
||||||
|
mtc0 t1, CP0_Status
|
||||||
|
}
|
||||||
128
inc/n64_vi.inc
Normal file
128
inc/n64_vi.inc
Normal file
|
|
@ -0,0 +1,128 @@
|
||||||
|
constant VI_BASE($A440) // $04400000..$04400037 Video Interface (VI) Base Register
|
||||||
|
constant VI_STATUS($00) // $04400000..$04400003 VI: Status/Control Register
|
||||||
|
constant VI_ORIGIN($04) // $04400004..$04400007 VI: Origin Register
|
||||||
|
constant VI_WIDTH($08) // $04400008..$0440000B VI: Width Register
|
||||||
|
constant VI_V_INTR($0C) // $0440000C..$0440000F VI: Vertical Interrupt Register
|
||||||
|
constant VI_V_CURRENT_LINE($10) // $04400010..$04400013 VI: Current Vertical Line Register
|
||||||
|
constant VI_TIMING($14) // $04400014..$04400017 VI: Video Timing Register
|
||||||
|
constant VI_V_SYNC($18) // $04400018..$0440001B VI: Vertical Sync Register
|
||||||
|
constant VI_H_SYNC($1C) // $0440001C..$0440001F VI: Horizontal Sync Register
|
||||||
|
constant VI_H_SYNC_LEAP($20) // $04400020..$04400023 VI: Horizontal Sync Leap Register
|
||||||
|
constant VI_H_VIDEO($24) // $04400024..$04400027 VI: Horizontal Video Register
|
||||||
|
constant VI_V_VIDEO($28) // $04400028..$0440002B VI: Vertical Video Register
|
||||||
|
constant VI_V_BURST($2C) // $0440002C..$0440002F VI: Vertical Burst Register
|
||||||
|
constant VI_X_SCALE($30) // $04400030..$04400033 VI: X-Scale Register
|
||||||
|
constant VI_Y_SCALE($34) // $04400034..$04400037 VI: Y-Scale Register
|
||||||
|
|
||||||
|
constant BPP0($0000) // VI Status/Control: Color Depth Blank (No Data Or Sync) (Bit 0..1)
|
||||||
|
//*RESERVED*($0001) // VI Status/Control: Color Depth Reserved (Bit 0..1)
|
||||||
|
constant BPP16($0002) // VI Status/Control: Color Depth 16BPP R5/G5/B5/A1 (Bit 0..1)
|
||||||
|
constant BPP32($0003) // VI Status/Control: Color Depth 32BPP R8/G8/B8/A8 (Bit 0..1)
|
||||||
|
constant GAMMA_DITHER_EN($00004) // VI Status/Control: Gamma Dither Enable (Requires: Gamma Enable) (Bit 2)
|
||||||
|
constant GAMMA_EN($00008) // VI Status/Control: Gamma Enable (Gamma Boost For YUV Images) (Bit 3)
|
||||||
|
constant DIVOT_EN($00010) // VI Status/Control: Divot Enable (Used With Anti-alias) (Bit 4)
|
||||||
|
constant VBUS_CLK_EN($00020) // VI Status/Control: Video Bus Clock Enable (Bit 5)
|
||||||
|
constant INTERLACE($00040) // VI Status/Control: Interlace/Serrate (Used With Interlaced Display) (Bit 6)
|
||||||
|
constant TST_MODE($00080) // VI Status/Control: Test Mode (Bit 7)
|
||||||
|
constant AA_MODE_0($00000) // VI Status/Control: AA Mode 0 = Anti-alias & Resample (Always Fetch Extra Lines) (Bit 8..9)
|
||||||
|
constant AA_MODE_1($00100) // VI Status/Control: AA Mode 1 = Anti-alias & Resample (Fetch Extra Lines When Needed) (Bit 8..9)
|
||||||
|
constant AA_MODE_2($00200) // VI Status/Control: AA Mode 2 = Resample Only (Bit 8..9)
|
||||||
|
constant AA_MODE_3($00300) // VI Status/Control: AA Mode 3 = Replicate Pixels & No Interpolation (Bit 8..9)
|
||||||
|
constant DIAG_0($00400) // VI Status/Control: Diagnotic 0 (Bit 10..11)
|
||||||
|
constant DIAG_1($00800) // VI Status/Control: Diagnotic 1 (Bit 10..11)
|
||||||
|
constant PIXEL_ADV_0($00000) // VI Status/Control: Pixel Advance 0 (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_1($01000) // VI Status/Control: Pixel Advance 1 (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_2($02000) // VI Status/Control: Pixel Advance 2 (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_3($03000) // VI Status/Control: Pixel Advance 3 (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_4($04000) // VI Status/Control: Pixel Advance 4 (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_5($05000) // VI Status/Control: Pixel Advance 5 (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_6($06000) // VI Status/Control: Pixel Advance 6 (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_7($07000) // VI Status/Control: Pixel Advance 7 (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_8($08000) // VI Status/Control: Pixel Advance 8 (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_9($09000) // VI Status/Control: Pixel Advance 9 (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_A($0A000) // VI Status/Control: Pixel Advance A (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_B($0B000) // VI Status/Control: Pixel Advance B (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_C($0C000) // VI Status/Control: Pixel Advance C (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_D($0D000) // VI Status/Control: Pixel Advance D (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_E($0E000) // VI Status/Control: Pixel Advance E (Bit 12..15)
|
||||||
|
constant PIXEL_ADV_F($0F000) // VI Status/Control: Pixel Advance F (Bit 12..15)
|
||||||
|
constant DITHER_FILTER_EN($10000) // VI Status/Control: Dither Filter Enable (Used With 16BPP Display) (Bit 16)
|
||||||
|
|
||||||
|
constant VI_NTSC_CLOCK(48681812) // NTSC: Hz = 48.681812 MHz
|
||||||
|
constant VI_PAL_CLOCK(49656530) // PAL: Hz = 49.656530 MHz
|
||||||
|
constant VI_MPAL_CLOCK(48628316) // MPAL: Hz = 48.628316 MHz
|
||||||
|
|
||||||
|
macro ScreenNTSC(width,height, status, origin) {
|
||||||
|
lui a0,VI_BASE // A0 = VI Base Register ($A4400000)
|
||||||
|
li t0,{status} // T0 = Status/Control
|
||||||
|
sw t0,VI_STATUS(a0) // Store Status/Control To VI Status Register ($A4400000)
|
||||||
|
la t0,{origin} // T0 = Origin (Frame Buffer Origin In Bytes)
|
||||||
|
sw t0,VI_ORIGIN(a0) // Store Origin To VI Origin Register ($A4400004)
|
||||||
|
lli t0,{width} // T0 = Width (Frame Buffer Line Width In Pixels)
|
||||||
|
sw t0,VI_WIDTH(a0) // Store Width To VI Width Register ($A4400008)
|
||||||
|
lli t0,$200 // T0 = Vertical Interrupt (Interrupt When Current Half-Line $200)
|
||||||
|
sw t0,VI_V_INTR(a0) // Store Vertical Interrupt To VI Interrupt Register ($A440000C)
|
||||||
|
lli t0,0 // T0 = Current Vertical Line (Current Half-Line, Sampled Once Per Line = 0)
|
||||||
|
sw t0,VI_V_CURRENT_LINE(a0) // Store Current Vertical Line To VI Current Register ($A4400010)
|
||||||
|
li t0,$3E52239 // T0 = Video Timing (Start Of Color Burst In Pixels from H-Sync = 3, Vertical Sync Width In Half Lines = 229, Color Burst Width In Pixels = 34, Horizontal Sync Width In Pixels = 57)
|
||||||
|
sw t0,VI_TIMING(a0) // Store Video Timing To VI Burst Register ($A4400014)
|
||||||
|
lli t0,$20D // T0 = Vertical Sync (Number Of Half-Lines Per Field = 525)
|
||||||
|
sw t0,VI_V_SYNC(a0) // Store Vertical Sync To VI V Sync Register ($A4400018)
|
||||||
|
lli t0,$C15 // T0 = Horizontal Sync (5-bit Leap Pattern Used For PAL only = 0, Total Duration Of A Line In 1/4 Pixel = 3093)
|
||||||
|
sw t0,VI_H_SYNC(a0) // Store Horizontal Sync To VI H Sync Register ($A440001C)
|
||||||
|
li t0,$C150C15 // T0 = Horizontal Sync Leap (Identical To H Sync = 3093, Identical To H Sync = 3093)
|
||||||
|
sw t0,VI_H_SYNC_LEAP(a0) // Store Horizontal Sync Leap To VI Leap Register ($A4400020)
|
||||||
|
li t0,$6C02EC // T0 = Horizontal Video (Start Of Active Video In Screen Pixels = 108, End Of Active Video In Screen Pixels = 748)
|
||||||
|
sw t0,VI_H_VIDEO(a0) // Store Horizontal Video To VI H Start Register ($A4400024)
|
||||||
|
li t0,$2501FF // T0 = Vertical Video (Start Of Active Video In Screen Half-Lines = 37, End Of Active Video In Screen Half-Lines = 511)
|
||||||
|
sw t0,VI_V_VIDEO(a0) // Store Vertical Video To VI V Start Register ($A4400028)
|
||||||
|
li t0,$E0204 // T0 = Vertical Burst (Start Of Color Burst Enable In Half-Lines = 14, End Of Color Burst Enable In Half-Lines = 516)
|
||||||
|
sw t0,VI_V_BURST(a0) // Store Vertical Burst To VI V Burst Register ($A440002C)
|
||||||
|
lli t0,($100*({width}/160)) // T0 = X-Scale (Horizontal Subpixel Offset In 2.10 Format = 0, 1/Horizontal Scale Up Factor In 2.10 Format)
|
||||||
|
sw t0,VI_X_SCALE(a0) // Store X-Scale To VI X Scale Register ($A4400030)
|
||||||
|
lli t0,($100*({height}/60)) // T0 = Y-Scale (Vertical Subpixel Offset In 2.10 Format = 0, 1/Vertical Scale Up Factor In 2.10 Format)
|
||||||
|
sw t0,VI_Y_SCALE(a0) // Store Y-Scale To VI Y Scale Register ($A4400034)
|
||||||
|
}
|
||||||
|
|
||||||
|
macro ScreenPAL(width,height, status, origin) {
|
||||||
|
lui a0,VI_BASE // A0 = VI Base Register ($A4400000)
|
||||||
|
la t0,{origin} // T0 = Origin (Frame Buffer Origin In Bytes)
|
||||||
|
sw t0,VI_ORIGIN(a0) // Store Origin To VI Origin Register ($A4400004)
|
||||||
|
lli t0,{width} // T0 = Width (Frame Buffer Line Width In Pixels)
|
||||||
|
sw t0,VI_WIDTH(a0) // Store Width To VI Width Register ($A4400008)
|
||||||
|
lli t0,$200 // T0 = Vertical Interrupt (Interrupt When Current Half-Line $200)
|
||||||
|
//lli t0,2
|
||||||
|
sw t0,VI_V_INTR(a0) // Store Vertical Interrupt To VI Interrupt Register ($A440000C)
|
||||||
|
lli t0,0 // T0 = Current Vertical Line (Current Half-Line, Sampled Once Per Line = 0)
|
||||||
|
sw t0,VI_V_CURRENT_LINE(a0) // Store Current Vertical Line To VI Current Register ($A4400010)
|
||||||
|
li t0,$404233A // T0 = Video Timing (Start Of Color Burst In Pixels from H-Sync = 4, Vertical Sync Width In Half Lines = 04, Color Burst Width In Pixels = 35, Horizontal Sync Width In Pixels = 58)
|
||||||
|
sw t0,VI_TIMING(a0) // Store Video Timing To VI Burst Register ($A4400014)
|
||||||
|
lli t0,$271 // T0 = Vertical Sync (Number Of Half-Lines Per Field = 625)
|
||||||
|
sw t0,VI_V_SYNC(a0) // Store Vertical Sync To VI V Sync Register ($A4400018)
|
||||||
|
li t0,$150C69 // T0 = Horizontal Sync (5-bit Leap Pattern Used For PAL only = 21: %10101, Total Duration Of A Line In 1/4 Pixel = 3177)
|
||||||
|
sw t0,VI_H_SYNC(a0) // Store Horizontal Sync To VI H Sync Register ($A440001C)
|
||||||
|
li t0,$C6F0C6E // T0 = Horizontal Sync Leap (Identical To H Sync = 3183, Identical To H Sync = 3182)
|
||||||
|
sw t0,VI_H_SYNC_LEAP(a0) // Store Horizontal Sync Leap To VI Leap Register ($A4400020)
|
||||||
|
li t0,$800300 // T0 = Horizontal Video (Start Of Active Video In Screen Pixels = 128, End Of Active Video In Screen Pixels = 768)
|
||||||
|
sw t0,VI_H_VIDEO(a0) // Store Horizontal Video To VI H Start Register ($A4400024)
|
||||||
|
li t0,$5F0239 // T0 = Vertical Video (Start Of Active Video In Screen Half-Lines = 95, End Of Active Video In Screen Half-Lines = 569)
|
||||||
|
sw t0,VI_V_VIDEO(a0) // Store Vertical Video To VI V Start Register ($A4400028)
|
||||||
|
li t0,$9026B // T0 = Vertical Burst (Start Of Color Burst Enable In Half-Lines = 9, End Of Color Burst Enable In Half-Lines = 619)
|
||||||
|
sw t0,VI_V_BURST(a0) // Store Vertical Burst To VI V Burst Register ($A440002C)
|
||||||
|
lli t0,($100*({width}/160)) // T0 = X-Scale (Horizontal Subpixel Offset In 2.10 Format = 0, 1/Horizontal Scale Up Factor In 2.10 Format)
|
||||||
|
sw t0,VI_X_SCALE(a0) // Store X-Scale To VI X Scale Register ($A4400030)
|
||||||
|
lli t0,($100*({height}/60)) // T0 = Y-Scale (Vertical Subpixel Offset In 2.10 Format = 0, 1/Vertical Scale Up Factor In 2.10 Format)
|
||||||
|
sw t0,VI_Y_SCALE(a0) // Store Y-Scale To VI Y Scale Register ($A4400034)
|
||||||
|
li t0,{status} // T0 = Status/Control
|
||||||
|
sw t0,VI_STATUS(a0) // Store Status/Control To VI Status Register ($A4400000)
|
||||||
|
}
|
||||||
|
|
||||||
|
macro WaitScanline(scanline) { // Wait For RDP To Reach Scanline
|
||||||
|
lui a0,VI_BASE // A0 = VI Base Register ($A4400000)
|
||||||
|
lli t0,{scanline} // T0 = Scan Line
|
||||||
|
-
|
||||||
|
lw t1,VI_V_CURRENT_LINE(a0) // T1 = Current Scan Line
|
||||||
|
bne t1,t0,- // IF (Current Scan Line != Scan Line) Wait
|
||||||
|
nop // ELSE Continue (Delay Slot)
|
||||||
|
}
|
||||||
|
|
||||||
14
inc/util.inc
Normal file
14
inc/util.inc
Normal file
|
|
@ -0,0 +1,14 @@
|
||||||
|
macro align(size) { // Align Byte Amount
|
||||||
|
while (pc() % {size}) {
|
||||||
|
db 0
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
macro nops(new_pc) {
|
||||||
|
if (pc() > {new_pc}) {
|
||||||
|
error "PC is already past the point specified"
|
||||||
|
}
|
||||||
|
while (pc() < {new_pc}) {
|
||||||
|
nop
|
||||||
|
}
|
||||||
|
}
|
||||||
28
main.asm
28
main.asm
|
|
@ -2,8 +2,8 @@
|
||||||
arch n64.cpu
|
arch n64.cpu
|
||||||
endian msb
|
endian msb
|
||||||
|
|
||||||
|
include "inc/util.inc"
|
||||||
include "inc/n64.inc"
|
include "inc/n64.inc"
|
||||||
include "inc/n64_gfx.inc"
|
|
||||||
include "inc/64drive.inc"
|
include "inc/64drive.inc"
|
||||||
include "inc/main.inc"
|
include "inc/main.inc"
|
||||||
include "inc/kernel.inc"
|
include "inc/kernel.inc"
|
||||||
|
|
@ -21,32 +21,6 @@ insert "bin/6102.bin"
|
||||||
|
|
||||||
include "kernel.asm"
|
include "kernel.asm"
|
||||||
|
|
||||||
macro EnableInt() {
|
|
||||||
lli t0, 0xAAA
|
|
||||||
lli t1, 0xFF01
|
|
||||||
lui a0, MI_BASE
|
|
||||||
sw t0, MI_INTR_MASK(a0)
|
|
||||||
mtc0 t1, CP0_Status
|
|
||||||
}
|
|
||||||
|
|
||||||
macro DisableInt() {
|
|
||||||
lli t0, 0x555
|
|
||||||
lli t1, 0x0001
|
|
||||||
lui a0, MI_BASE
|
|
||||||
sw t0, MI_INTR_MASK(a0)
|
|
||||||
mtc0 t1, CP0_Status
|
|
||||||
}
|
|
||||||
|
|
||||||
macro SP_BUSY_WAIT() {
|
|
||||||
lui a0, SP_BASE
|
|
||||||
-
|
|
||||||
lw t0, SP_STATUS(a0)
|
|
||||||
andi t0, 0x1C
|
|
||||||
sltu t0, r0, t0 // TODO: rewrite this
|
|
||||||
bnez t0,-
|
|
||||||
nop
|
|
||||||
}
|
|
||||||
|
|
||||||
Main:
|
Main:
|
||||||
lui t0, K_BASE
|
lui t0, K_BASE
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue