rename SP constants
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4 changed files with 146 additions and 146 deletions
206
F3DZEX.asm
206
F3DZEX.asm
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@ -33,67 +33,67 @@ macro nops(new_pc) {
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// when we're in the RSP, the registers accessible by mtc0/mfc0
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// are the ones associated with the RSP. they are memory-mapped as well.
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constant SP_COP_MEM_ADDR(0) // 0x04040000
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constant SP_COP_DRAM_ADDR(1) // 0x04040004
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constant SP_COP_RD_LEN(2) // 0x04040008
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constant SP_COP_WR_LEN(3) // 0x0404000C
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constant SP_COP_STATUS(4) // 0x04040010
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constant SP_COP_DMA_FULL(5) // 0x04040014
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constant SP_COP_DMA_BUSY(6) // 0x04040018
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constant SP_COP_SEMAPHORE(7) // 0x0404001C
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constant MEM_ADDR(0) // 0x04040000
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constant DRAM_ADDR(1) // 0x04040004
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constant RD_LEN(2) // 0x04040008
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constant WR_LEN(3) // 0x0404000C
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constant STATUS(4) // 0x04040010
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constant DMA_FULL(5) // 0x04040014
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constant DMA_BUSY(6) // 0x04040018
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constant SEMAPHORE(7) // 0x0404001C
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// RDP registers:
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constant SP_COP_COMMAND_START(8) // 0x04100000
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constant SP_COP_COMMAND_END(9) // 0x04100004
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constant SP_COP_COMMAND_CURRENT(10) // 0x04100008
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constant SP_COP_RDP_STATUS(11) // 0x0410000C
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constant SP_COP_COUNT(12) // 0x04100010
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constant SP_COP_COMMAND_BUSY(13) // 0x04100014
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constant SP_COP_PIPE_BUSY(14) // 0x04100018
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constant SP_COP_TMEM_BUSY(15) // 0x0410001C
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constant COMMAND_START(8) // 0x04100000
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constant COMMAND_END(9) // 0x04100004
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constant COMMAND_CURRENT(10) // 0x04100008
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constant RDP_STATUS(11) // 0x0410000C
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constant COUNT(12) // 0x04100010
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constant COMMAND_BUSY(13) // 0x04100014
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constant PIPE_BUSY(14) // 0x04100018
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constant TMEM_BUSY(15) // 0x0410001C
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// SP_COP_STATUS Read Flags:
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constant SP_HLT($0001) // Halt
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constant SP_BRK($0002) // Break
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constant SP_BSY($0004) // DMA Busy
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constant SP_FUL($0008) // DMA Full
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constant SP_IOF($0010) // IO Full
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constant SP_STP($0020) // Single Step
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constant SP_IOB($0040) // Interrupt On Break
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constant SP_SG0($0080) // Signal 0 Set
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constant SP_SG1($0100) // Signal 1 Set
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constant SP_SG2($0200) // Signal 2 Set
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constant SP_SG3($0400) // Signal 3 Set
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constant SP_SG4($0800) // Signal 4 Set
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constant SP_SG5($1000) // Signal 5 Set
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constant SP_SG6($2000) // Signal 6 Set
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constant SP_SG7($4000) // Signal 7 Set
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// STATUS Read Flags:
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constant HLT($0001) // Halt
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constant BRK($0002) // Break
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constant BSY($0004) // DMA Busy
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constant FUL($0008) // DMA Full
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constant IOF($0010) // IO Full
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constant STP($0020) // Single Step
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constant IOB($0040) // Interrupt On Break
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constant SG0($0080) // Signal 0 Set
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constant SG1($0100) // Signal 1 Set
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constant SG2($0200) // Signal 2 Set
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constant SG3($0400) // Signal 3 Set
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constant SG4($0800) // Signal 4 Set
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constant SG5($1000) // Signal 5 Set
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constant SG6($2000) // Signal 6 Set
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constant SG7($4000) // Signal 7 Set
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// SP_COP_STATUS Write Flags:
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constant SP_CLR_HLT($00000001) // Clear Halt
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constant SP_SET_HLT($00000002) // Set Halt
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constant SP_CLR_BRK($00000004) // Clear Broke
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constant SP_CLR_INT($00000008) // Clear Interrupt
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constant SP_SET_INT($00000010) // Set Interrupt
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constant SP_CLR_STP($00000020) // Clear Single Step
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constant SP_SET_STP($00000040) // Set Single Step
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constant SP_CLR_IOB($00000080) // Clear Interrupt On Break
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constant SP_SET_IOB($00000100) // Set Interrupt On Break
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constant SP_CLR_SG0($00000200) // Clear Signal 0
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constant SP_SET_SG0($00000400) // Set Signal 0
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constant SP_CLR_SG1($00000800) // Clear Signal 1
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constant SP_SET_SG1($00001000) // Set Signal 1
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constant SP_CLR_SG2($00002000) // Clear Signal 2
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constant SP_SET_SG2($00004000) // Set Signal 2
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constant SP_CLR_SG3($00008000) // Clear Signal 3
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constant SP_SET_SG3($00010000) // Set Signal 3
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constant SP_CLR_SG4($00020000) // Clear Signal 4
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constant SP_SET_SG4($00040000) // Set Signal 4
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constant SP_CLR_SG5($00080000) // Clear Signal 5
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constant SP_SET_SG5($00100000) // Set Signal 5
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constant SP_CLR_SG6($00200000) // Clear Signal 6
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constant SP_SET_SG6($00400000) // Set Signal 6
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constant SP_CLR_SG7($00800000) // Clear Signal 7
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constant SP_SET_SG7($01000000) // Set Signal 7
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// STATUS Write Flags:
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constant HLT_CLR($00000001) // Clear Halt
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constant HLT_SET($00000002) // Set Halt
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constant BRK_CLR($00000004) // Clear Broke
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constant INT_CLR($00000008) // Clear Interrupt
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constant INT_SET($00000010) // Set Interrupt
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constant STP_CLR($00000020) // Clear Single Step
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constant STP_SET($00000040) // Set Single Step
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constant IOB_CLR($00000080) // Clear Interrupt On Break
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constant IOB_SET($00000100) // Set Interrupt On Break
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constant SG0_CLR($00000200) // Clear Signal 0
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constant SG0_SET($00000400) // Set Signal 0
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constant SG1_CLR($00000800) // Clear Signal 1
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constant SG1_SET($00001000) // Set Signal 1
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constant SG2_CLR($00002000) // Clear Signal 2
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constant SG2_SET($00004000) // Set Signal 2
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constant SG3_CLR($00008000) // Clear Signal 3
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constant SG3_SET($00010000) // Set Signal 3
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constant SG4_CLR($00020000) // Clear Signal 4
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constant SG4_SET($00040000) // Set Signal 4
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constant SG5_CLR($00080000) // Clear Signal 5
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constant SG5_SET($00100000) // Set Signal 5
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constant SG6_CLR($00200000) // Clear Signal 6
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constant SG6_SET($00400000) // Set Signal 6
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constant SG7_CLR($00800000) // Clear Signal 7
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constant SG7_SET($01000000) // Set Signal 7
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// Task Struct:
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constant TASK_START(0xFC0)
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@ -128,31 +128,31 @@ label_1008:
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lw v0, TASK_UCODE-TASK_START(at)
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addi v1, r0, 0x0F7F // copy 0xF80 bytes
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addi a3, r0, 0x1080 // to 0xA4001080
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mtc0 a3, SP_COP_MEM_ADDR
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mtc0 v0, SP_COP_DRAM_ADDR
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mtc0 v1, SP_COP_RD_LEN // start the DMA
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mtc0 a3, MEM_ADDR
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mtc0 v0, DRAM_ADDR
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mtc0 v1, RD_LEN // start the DMA
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label_1020:
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-
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mfc0 a0, SP_COP_DMA_BUSY // wait until it finishes
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mfc0 a0, DMA_BUSY // wait until it finishes
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bnez a0,-
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nop
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jal func_103C // check error status
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nop
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jr a3 // jump to the new code we just loaded
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mtc0 r0, SP_COP_SEMAPHORE
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mtc0 r0, SEMAPHORE
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func_103C:
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mfc0 t0, SP_COP_STATUS
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mfc0 t0, STATUS
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label_1040:
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andi t0, t0, 1<<7 // check flag 7: signal 0 set
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bnez t0,+ // branch if signal 0 is set
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nop
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jr ra
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+
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mtc0 r0, SP_COP_SEMAPHORE
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ori t0, r0, SP_CLR_SG0 | SP_SET_SG1 | SP_SET_SG2
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mtc0 t0, SP_COP_STATUS
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mtc0 r0, SEMAPHORE
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ori t0, r0, SG0_CLR | SG1_SET | SG2_SET
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mtc0 t0, STATUS
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break 0
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nop
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@ -163,7 +163,7 @@ label_1054:
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nop
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jal func_103C
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nop
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mfc0 v0, SP_COP_RDP_STATUS
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mfc0 v0, RDP_STATUS
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// note: this marks 0x80, meaning everything below gets overwritten later.
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andi v0, v0, 0x0100
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@ -174,14 +174,14 @@ label_1054:
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lw v1, TASK_UCODE_DATA_SIZE-TASK_START(at)
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subi v1, v1, 1 // subtract 1 for DMA quirk
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-
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mfc0 fp, SP_COP_DMA_FULL
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mfc0 fp, DMA_FULL
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bnez fp,- // wait until the last DMA is finished?
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nop
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mtc0 r0, SP_COP_MEM_ADDR // target: A4000000 (DMEM)
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mtc0 v0, SP_COP_DRAM_ADDR
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mtc0 v1, SP_COP_RD_LEN // start the DMA
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mtc0 r0, MEM_ADDR // target: A4000000 (DMEM)
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mtc0 v0, DRAM_ADDR
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mtc0 v1, RD_LEN // start the DMA
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-
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mfc0 a0, SP_COP_DMA_BUSY // wait until it finishes
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mfc0 a0, DMA_BUSY // wait until it finishes
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bnez a0,-
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nop
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jal func_103C // check error status
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@ -209,9 +209,9 @@ func_1088:
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vsub vec1,vec0,vec31[e8]
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lw t3, 0x0F0(r0) // TASK_DRAM_STACK gets written here?
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lw t4, TASK_FLAGS(r0)
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addi at, r0, SP_CLR_SG1 | SP_CLR_SG2
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addi at, r0, SG1_CLR | SG2_CLR
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beqz t3,+
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mtc0 at, SP_COP_STATUS
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mtc0 at, STATUS
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andi t4, t4, 1 // check if flag 0 is set
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beqz t4,label_1130
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@ -221,15 +221,15 @@ func_1088:
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lw k0, 0xBF8(r0)
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+
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mfc0 t3, SP_COP_RDP_STATUS
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mfc0 t3, RDP_STATUS
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andi t3, t3, 1
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bnez t3,+
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mfc0 v0, SP_COP_COMMAND_END
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mfc0 v0, COMMAND_END
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lw v1, TASK_OUTPUT_BUFF(r0)
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sub t3, v1, v0
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bgtz t3,+
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mfc0 at, SP_COP_COMMAND_CURRENT
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mfc0 at, COMMAND_CURRENT
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lw a0, TASK_OUTPUT_BUFF_SIZE(r0)
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beqz at,+
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@ -241,16 +241,16 @@ func_1088:
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bne at, v0,++
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+
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-
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mfc0 t3, SP_COP_RDP_STATUS
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mfc0 t3, RDP_STATUS
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andi t3, t3, 0x0400
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bnez t3,-
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addi t3, r0, 1
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mtc0 t3, SP_COP_RDP_STATUS
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mtc0 t3, RDP_STATUS
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lw v0, TASK_OUTPUT_BUFF_SIZE(r0)
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mtc0 v0, SP_COP_COMMAND_START
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mtc0 v0, SP_COP_COMMAND_END
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mtc0 v0, COMMAND_START
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mtc0 v0, COMMAND_END
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+
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sw v0, 0x0F0(r0)
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lw t3, 0x0F4(r0)
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@ -293,11 +293,11 @@ label_1188:
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label_1190:
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jal func_1FC8
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label_1194:
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mfc0 at, SP_COP_STATUS
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mfc0 at, STATUS
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lw t9, 0x09C8(k1)
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beqz k1,label_1178
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label_11A0:
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andi at, at, SP_SG0
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andi at, at, SG0
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label_11A4:
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sra t4, t9, 24
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@ -307,7 +307,7 @@ label_11A4:
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lw t8, 0x09CC(k1)
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jr t3
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addiu k1, k1, SP_COP_COMMAND_START
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addiu k1, k1, COMMAND_START
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jal func_1224
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lh s4, 0x09C1(k1)
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@ -332,13 +332,13 @@ label_11EC:
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ldv vec29[e0], 0x0D0(r0)
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lw t9, 0x0D8(r0)
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addi s7, s7, SP_COP_COMMAND_START
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addi s7, s7, COMMAND_START
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sdv vec29[e0], 0x3F8(s7)
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label_1210:
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sw t8, 0x4(s7)
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sw t9, 0x0(s7)
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j label_1258
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addi s7, s7, SP_COP_COMMAND_START
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addi s7, s7, COMMAND_START
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addi ra, r0, label_1210
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func_1224:
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@ -363,32 +363,32 @@ label_125C:
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sub t3, s7, s6
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blez t3, label_1FD4
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label_1264:
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mfc0 t4, SP_COP_DMA_BUSY
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mfc0 t4, DMA_BUSY
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lw t8, 0x0F0(r0)
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addiu s3, t3, 0x0158
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bnez t4,label_1264
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lw t4, TASK_OUTPUT_BUFF_SIZE(r0)
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mtc0 t8, SP_COP_COMMAND_END
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mtc0 t8, COMMAND_END
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add t3, t8, s3
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sub t4, t4, t3
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bgez t4,+
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-
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mfc0 t3, SP_COP_RDP_STATUS
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mfc0 t3, RDP_STATUS
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andi t3, t3, 0x0400
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bnez t3,-
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lw t8, TASK_OUTPUT_BUFF(r0)
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-
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mfc0 t3, SP_COP_COMMAND_CURRENT
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mfc0 t3, COMMAND_CURRENT
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beq t3, t8,-
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nop
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mtc0 t8, SP_COP_COMMAND_START
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mtc0 t8, COMMAND_START
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+
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-
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mfc0 t3, SP_COP_COMMAND_CURRENT
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mfc0 t3, COMMAND_CURRENT
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sub t3, t3, t8
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blez t3,+
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@ -1103,25 +1103,25 @@ func_1FB4:
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lhu s4, 0x6(t3)
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ori ra, t4, 0x0
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func_1FC8:
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mfc0 t3, SP_COP_DMA_BUSY
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mfc0 t3, DMA_BUSY
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-
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bnez t3,-
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mfc0 t3, SP_COP_DMA_BUSY
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mfc0 t3, DMA_BUSY
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label_1FD4:
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jr ra
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func_1FD8:
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mfc0 t3, SP_COP_DMA_FULL
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mfc0 t3, DMA_FULL
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-
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bnez t3,-
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mfc0 t3, SP_COP_DMA_FULL
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mtc0 s4, SP_COP_MEM_ADDR
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mfc0 t3, DMA_FULL
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mtc0 s4, MEM_ADDR
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bltz s4,+
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mtc0 t8, SP_COP_DRAM_ADDR
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mtc0 t8, DRAM_ADDR
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jr ra
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mtc0 s3, SP_COP_RD_LEN
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mtc0 s3, RD_LEN
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+
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jr ra
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mtc0 s3, SP_COP_WR_LEN
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mtc0 s3, WR_LEN
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// this gets loaded by func_1FB4 from DMEM+$2E0
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base 0x1000
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@ -1133,7 +1133,7 @@ base 0x1000
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jal func_1FC8
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lw t8, 0x0F0(r0)
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bltz at, label_1084
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mtc0 t8, SP_COP_COMMAND_END
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mtc0 t8, COMMAND_END
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bnez at, label_1060
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add k0, k0, k1
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lw t8, 0x09C4(k1)
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@ -1163,7 +1163,7 @@ label_1060:
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addi ra, r0, func_1088
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addi t4, r0, 0x4000
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mtc0 t4, SP_COP_STATUS
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mtc0 t4, STATUS
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break 0x00000
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nop
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nop
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@ -17,48 +17,48 @@ constant SP_PC($00) // $04080000..$04080003 SP: PC Register
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constant SP_IBIST_REG($04) // $04080004..$04080007 SP: IMEM BIST Register
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// SP_STATUS Read Flags:
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constant RSP_HLT($0001) // Halt
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constant RSP_BRK($0002) // Break
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constant RSP_BSY($0004) // DMA Busy
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constant RSP_FUL($0008) // DMA Full
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constant RSP_IOF($0010) // IO Full
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constant RSP_STP($0020) // Single Step
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constant RSP_IOB($0040) // Interrupt On Break
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constant RSP_SG0($0080) // Signal 0 Set
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constant RSP_SG1($0100) // Signal 1 Set
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constant RSP_SG2($0200) // Signal 2 Set
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constant RSP_SG3($0400) // Signal 3 Set
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constant RSP_SG4($0800) // Signal 4 Set
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constant RSP_SG5($1000) // Signal 5 Set
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constant RSP_SG6($2000) // Signal 6 Set
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constant RSP_SG7($4000) // Signal 7 Set
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constant SP_HLT($0001) // Halt
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constant SP_BRK($0002) // Break
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constant SP_BSY($0004) // DMA Busy
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constant SP_FUL($0008) // DMA Full
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constant SP_IOF($0010) // IO Full
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constant SP_STP($0020) // Single Step
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constant SP_IOB($0040) // Interrupt On Break
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constant SP_SG0($0080) // Signal 0 Set
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constant SP_SG1($0100) // Signal 1 Set
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constant SP_SG2($0200) // Signal 2 Set
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constant SP_SG3($0400) // Signal 3 Set
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constant SP_SG4($0800) // Signal 4 Set
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constant SP_SG5($1000) // Signal 5 Set
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constant SP_SG6($2000) // Signal 6 Set
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constant SP_SG7($4000) // Signal 7 Set
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||||
// SP_STATUS Write Flags:
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constant CLR_HLT($00000001) // Clear Halt
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||||
constant SET_HLT($00000002) // Set Halt
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||||
constant CLR_BRK($00000004) // Clear Broke
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constant CLR_INT($00000008) // Clear Interrupt
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constant SET_INT($00000010) // Set Interrupt
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constant CLR_STP($00000020) // Clear Single Step
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||||
constant SET_STP($00000040) // Set Single Step
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||||
constant CLR_IOB($00000080) // Clear Interrupt On Break
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constant SET_IOB($00000100) // Set Interrupt On Break
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||||
constant CLR_SG0($00000200) // Clear Signal 0
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||||
constant SET_SG0($00000400) // Set Signal 0
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||||
constant CLR_SG1($00000800) // Clear Signal 1
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constant SET_SG1($00001000) // Set Signal 1
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constant CLR_SG2($00002000) // Clear Signal 2
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constant SET_SG2($00004000) // Set Signal 2
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||||
constant CLR_SG3($00008000) // Clear Signal 3
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constant SET_SG3($00010000) // Set Signal 3
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constant CLR_SG4($00020000) // Clear Signal 4
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||||
constant SET_SG4($00040000) // Set Signal 4
|
||||
constant CLR_SG5($00080000) // Clear Signal 5
|
||||
constant SET_SG5($00100000) // Set Signal 5
|
||||
constant CLR_SG6($00200000) // Clear Signal 6
|
||||
constant SET_SG6($00400000) // Set Signal 6
|
||||
constant CLR_SG7($00800000) // Clear Signal 7
|
||||
constant SET_SG7($01000000) // Set Signal 7
|
||||
constant SP_HLT_CLR($00000001) // Clear Halt
|
||||
constant SP_HLT_SET($00000002) // Set Halt
|
||||
constant SP_BRK_CLR($00000004) // Clear Broke
|
||||
constant SP_INT_CLR($00000008) // Clear Interrupt
|
||||
constant SP_INT_SET($00000010) // Set Interrupt
|
||||
constant SP_STP_CLR($00000020) // Clear Single Step
|
||||
constant SP_STP_SET($00000040) // Set Single Step
|
||||
constant SP_IOB_CLR($00000080) // Clear Interrupt On Break
|
||||
constant SP_IOB_SET($00000100) // Set Interrupt On Break
|
||||
constant SP_SG0_CLR($00000200) // Clear Signal 0
|
||||
constant SP_SG0_SET($00000400) // Set Signal 0
|
||||
constant SP_SG1_CLR($00000800) // Clear Signal 1
|
||||
constant SP_SG1_SET($00001000) // Set Signal 1
|
||||
constant SP_SG2_CLR($00002000) // Clear Signal 2
|
||||
constant SP_SG2_SET($00004000) // Set Signal 2
|
||||
constant SP_SG3_CLR($00008000) // Clear Signal 3
|
||||
constant SP_SG3_SET($00010000) // Set Signal 3
|
||||
constant SP_SG4_CLR($00020000) // Clear Signal 4
|
||||
constant SP_SG4_SET($00040000) // Set Signal 4
|
||||
constant SP_SG5_CLR($00080000) // Clear Signal 5
|
||||
constant SP_SG5_SET($00100000) // Set Signal 5
|
||||
constant SP_SG6_CLR($00200000) // Clear Signal 6
|
||||
constant SP_SG6_SET($00400000) // Set Signal 6
|
||||
constant SP_SG7_CLR($00800000) // Clear Signal 7
|
||||
constant SP_SG7_SET($01000000) // Set Signal 7
|
||||
|
||||
macro SP_DMA_WAIT() { // from CPU
|
||||
lui t5, SP_BASE
|
||||
|
|
|
|||
|
|
@ -457,7 +457,7 @@ K_MI_Loop:
|
|||
K_MI_SP:
|
||||
KMaybeDumpString(KS_MI_SP)
|
||||
|
||||
lli t0, CLR_SG3 | CLR_INT // delay slot
|
||||
lli t0, SP_SG3_CLR | SP_INT_CLR // delay slot
|
||||
lui a1, SP_BASE
|
||||
sw t0, SP_STATUS(a1)
|
||||
|
||||
|
|
|
|||
4
main.asm
4
main.asm
|
|
@ -91,7 +91,7 @@ Start3D:
|
|||
|
||||
// stuff i'm borrowing from zelda:
|
||||
lui a0, SP_BASE
|
||||
lli t0, CLR_SG2 | CLR_SG1 | CLR_SG0 | SET_IOB
|
||||
lli t0, SP_SG2_CLR | SP_SG1_CLR | SP_SG0_CLR | SP_IOB_SET
|
||||
sw t0, SP_STATUS(a0)
|
||||
|
||||
// wait
|
||||
|
|
@ -130,7 +130,7 @@ Start3D:
|
|||
|
||||
// clear all flags that would halt RSP (i.e. tell it to run!)
|
||||
lui a0, SP_BASE
|
||||
lli t0, SET_IOB | CLR_STP | CLR_BRK | CLR_HLT
|
||||
lli t0, SP_IOB_SET | SP_STP_CLR | SP_BRK_CLR | SP_HLT_CLR
|
||||
sw t0, SP_STATUS(a0)
|
||||
nop
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue