improve and reduce verbosity of system addresses
This commit is contained in:
parent
66ab443b9c
commit
8310f4aae7
11 changed files with 160 additions and 117 deletions
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@ -1,12 +1,13 @@
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// gMatrix: params argument
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// gMatrix: params argument
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// NOTE: the 0 flags are to declare intent. they have no effect.
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constant G_MTX_NOPUSH(0 << 0)
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constant G_MTX_MODELVIEW(0)
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constant G_MTX_PUSH(1 << 0)
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constant G_MTX_PROJECTION(4)
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//
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constant G_MTX_MUL(0)
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constant G_MTX_MUL(0 << 1)
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constant G_MTX_LOAD(2)
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constant G_MTX_LOAD(1 << 1)
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constant G_MTX_NOPUSH(0)
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//
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constant G_MTX_PUSH(1)
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constant G_MTX_MODELVIEW(0 << 2)
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constant G_MTX_PROJECTION(1 << 2)
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// gMoveWord: index argument
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// gMoveWord: index argument
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constant G_MW_MATRIX(0x0)
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constant G_MW_MATRIX(0x0)
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@ -69,15 +69,15 @@ if {dpos} >= 0x2000 {
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}
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}
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macro MatEye() {
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macro MatEye() {
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dh 0x0001, 0x0000, 0x0000, 0x0000
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dh 1, 0, 0, 0
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dh 0x0000, 0x0001, 0x0000, 0x0000
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dh 0, 1, 0, 0
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dh 0x0000, 0x0000, 0x0001, 0x0000
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dh 0, 0, 1, 0
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dh 0x0000, 0x0000, 0x0000, 0x0001
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dh 0, 0, 0, 1
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dh 0x0000, 0x0000, 0x0000, 0x0000
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dh 0, 0, 0, 0
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dh 0x0000, 0x0000, 0x0000, 0x0000
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dh 0, 0, 0, 0
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dh 0x0000, 0x0000, 0x0000, 0x0000
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dh 0, 0, 0, 0
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dh 0x0000, 0x0000, 0x0000, 0x0000
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dh 0, 0, 0, 0
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}
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}
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macro Matrix(variable xx, variable xy, variable xz, variable xw, variable yx, variable yy, variable yz, variable yw, variable zx, variable zy, variable zz, variable zw, variable wx, variable wy, variable wz, variable ww) {
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macro Matrix(variable xx, variable xy, variable xz, variable xw, variable yx, variable yy, variable yz, variable yw, variable zx, variable zy, variable zz, variable zw, variable wx, variable wy, variable wz, variable ww) {
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22
inc/n64.inc
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inc/n64.inc
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@ -16,14 +16,14 @@ include "n64_pif.inc"
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include "n64_util.inc"
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include "n64_util.inc"
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// Memory Map
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// Memory Map
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constant RDRAM_BASE($A3F0) // $03F00000..$03F00027 RDRAM Base Register
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constant RDRAM_BASE($A3F0) // $03F00000 RDRAM Base
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constant RDRAM_DEVICE_TYPE($00) // $03F00000..$03F00003 RDRAM: Device Type Register
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constant RDRAM_DEVICE_TYPE($00) // $03F00000 Device Type
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constant RDRAM_DEVICE_ID($04) // $03F00004..$03F00007 RDRAM: Device ID Register
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constant RDRAM_DEVICE_ID($04) // $03F00004 Device ID
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constant RDRAM_DELAY($08) // $03F00008..$03F0000B RDRAM: Delay Register
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constant RDRAM_DELAY($08) // $03F00008 Delay
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constant RDRAM_MODE($0C) // $03F0000C..$03F0000F RDRAM: Mode Register
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constant RDRAM_MODE($0C) // $03F0000C Mode
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constant RDRAM_REF_INTERVAL($10) // $03F00010..$03F00013 RDRAM: Ref Interval Register
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constant RDRAM_REF_INTERVAL($10) // $03F00010 Ref Interval
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constant RDRAM_REF_ROW($14) // $03F00014..$03F00017 RDRAM: Ref Row Register
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constant RDRAM_REF_ROW($14) // $03F00014 Ref Row
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constant RDRAM_RAS_INTERVAL($18) // $03F00018..$03F0001B RDRAM: Ras Interval Register
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constant RDRAM_RAS_INTERVAL($18) // $03F00018 Ras Interval
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constant RDRAM_MIN_INTERVAL($1C) // $03F0001C..$03F0001F RDRAM: Minimum Interval Register
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constant RDRAM_MIN_INTERVAL($1C) // $03F0001C Minimum Interval
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constant RDRAM_ADDR_SELECT($20) // $03F00020..$03F00023 RDRAM: Address Select Register
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constant RDRAM_ADDR_SELECT($20) // $03F00020 Address Select
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constant RDRAM_DEVICE_MANUF($24) // $03F00024..$03F00027 RDRAM: Device Manufacturer Register
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constant RDRAM_DEVICE_MANUF($24) // $03F00024 Device Manufacturer
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@ -1,16 +1,40 @@
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constant DPC_BASE($A410) // $04100000..$0410001F DP Command (DPC) Base Register
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constant DPC_BASE($A410) // $04100000 DP Command Base Register
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constant DPC_START($00) // $04100000..$04100003 DPC: CMD DMA Start Register
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constant DPC_START($00) // $04100000 CMD DMA Start Register
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constant DPC_END($04) // $04100004..$04100007 DPC: CMD DMA End Register
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constant DPC_END($04) // $04100004 CMD DMA End Register
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constant DPC_CURRENT($08) // $04100008..$0410000B DPC: CMD DMA Current Register
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constant DPC_CURRENT($08) // $04100008 CMD DMA Current Register
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constant DPC_STATUS($0C) // $0410000C..$0410000F DPC: CMD Status Register
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constant DPC_STATUS($0C) // $0410000C CMD Status Register
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constant DPC_CLOCK($10) // $04100010..$04100013 DPC: Clock Counter Register
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constant DPC_CLOCK($10) // $04100010 Clock Counter Register
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constant DPC_BUFBUSY($14) // $04100014..$04100017 DPC: Buffer Busy Counter Register
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constant DPC_BUFBUSY($14) // $04100014 Buffer Busy Counter Register
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constant DPC_PIPEBUSY($18) // $04100018..$0410001B DPC: Pipe Busy Counter Register
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constant DPC_PIPEBUSY($18) // $04100018 Pipe Busy Counter Register
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constant DPC_TMEM($1C) // $0410001C..$0410001F DPC: TMEM Load Counter Register
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constant DPC_TMEM($1C) // $0410001C TMEM Load Counter Register
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constant DPS_BASE($A420) // $04200000..$0420000F DP Span (DPS) Base Register
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constant DPS_BASE($A420) // $04200000 DP Span Base Register
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constant DPS_TBIST($00) // $04200000..$04200003 DPS: Tmem Bist Register
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constant DPS_TBIST($00) // $04200000 Tmem Bist Register
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constant DPS_TEST_MODE($04) // $04200004..$04200007 DPS: Span Test Mode Register
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constant DPS_TEST_MODE($04) // $04200004 Span Test Mode Register
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constant DPS_BUFTEST_ADDR($08) // $04200008..$0420000B DPS: Span Buffer Test Address Register
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constant DPS_BUFTEST_ADDR($08) // $04200008 Span Buffer Test Address Register
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constant DPS_BUFTEST_DATA($0C) // $0420000C..$0420000F DPS: Span Buffer Test Data Register
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constant DPS_BUFTEST_DATA($0C) // $0420000C Span Buffer Test Data Register
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// DPC_STATUS Read Flags:
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constant DPC_XBS($001) // Use XBUS DMEM DMA Or DRAM DMA (Bit 0)
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constant DPC_FRZ($002) // RDP Frozen (Bit 1)
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constant DPC_FLUSH($004) // RDP Flushed (Bit 2)
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constant DPC_GCL($008) // GCLK Alive (Bit 3)
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constant DPC_TMB($010) // TMEM Busy (Bit 4)
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constant DPC_PLB($020) // RDP PIPELINE Busy (Bit 5)
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constant DPC_CMB($040) // RDP COMMAND Unit Busy (Bit 6)
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constant DPC_CMR($080) // RDP COMMAND Buffer Ready (Bit 7)
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constant DPC_DMA($100) // RDP DMA Busy (Bit 8)
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constant DPC_CME($200) // RDP COMMAND END Register Valid (Bit 9)
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constant DPC_CMS($400) // RDP COMMAND START Register Valid (Bit 10)
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// DPC_STATUS Write Flags:
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constant DPC_XBS_CLR($001) // Clear XBUS DMEM DMA (Bit 0)
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constant DPC_XBS_SET($002) // Set XBUS DMEM DMA (Bit 1)
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constant DPC_FRZ_CLR($004) // Clear FREEZE (Bit 2)
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constant DPC_FRZ_SET($008) // Set FREEZE (Bit 3)
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constant DPC_FLUSH_CLR($010) // Clear FLUSH (Bit 4)
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constant DPC_FLUSH_SET($020) // Set FLUSH (Bit 5)
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constant DPC_TMC_CLR($040) // Clear TMEM COUNTER (Bit 6)
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constant DPC_PLC_CLR($080) // Clear PIPELINE COUNTER (Bit 7)
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constant DPC_CMC_CLR($100) // Clear COMMAND COUNTER (Bit 8)
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constant DPC_CLK_CLR($200) // Clear CLOCK COUNTER (Bit 9)
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@ -1,17 +1,17 @@
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constant PI_BASE($A460) // $04600000..$04600033 Peripheral Interface (PI) Base Register
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constant PI_BASE($A460) // $04600000..$04600033 Peripheral Interface (PI) Base
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constant PI_DRAM_ADDR($00) // $04600000..$04600003 PI: DRAM Address Register
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constant PI_DRAM_ADDR($00) // $04600000 DRAM Address
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constant PI_CART_ADDR($04) // $04600004..$04600007 PI: Pbus (Cartridge) Address Register
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constant PI_CART_ADDR($04) // $04600004 Pbus (Cartridge) Address
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constant PI_RD_LEN($08) // $04600008..$0460000B PI: Read Length Register
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constant PI_RD_LEN($08) // $04600008 Read Length
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constant PI_WR_LEN($0C) // $0460000C..$0460000F PI: Write length register
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constant PI_WR_LEN($0C) // $0460000C Write Length
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constant PI_STATUS($10) // $04600010..$04600013 PI: Status Register
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constant PI_STATUS($10) // $04600010 Status
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constant PI_BSD_DOM1_LAT($14) // $04600014..$04600017 PI: Domain 1 Latency Register
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constant PI_BSD_DOM1_LAT($14) // $04600014 Domain 1 Latency
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constant PI_BSD_DOM1_PWD($18) // $04600018..$0460001B PI: Domain 1 Pulse Width Register
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constant PI_BSD_DOM1_PWD($18) // $04600018 Domain 1 Pulse Width
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constant PI_BSD_DOM1_PGS($1C) // $0460001C..$0460001F PI: Domain 1 Page Size Register
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constant PI_BSD_DOM1_PGS($1C) // $0460001C Domain 1 Page Size
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constant PI_BSD_DOM1_RLS($20) // $04600020..$04600023 PI: Domain 1 Release Register
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constant PI_BSD_DOM1_RLS($20) // $04600020 Domain 1 Release
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constant PI_BSD_DOM2_LAT($24) // $04600024..$04600027 PI: Domain 2 Latency Register
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constant PI_BSD_DOM2_LAT($24) // $04600024 Domain 2 Latency
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constant PI_BSD_DOM2_PWD($28) // $04600028..$0460002B PI: Domain 2 Pulse Width Register
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constant PI_BSD_DOM2_PWD($28) // $04600028 Domain 2 Pulse Width
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constant PI_BSD_DOM2_PGS($2C) // $0460002C..$0460002F PI: Domain 2 Page Size Register
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constant PI_BSD_DOM2_PGS($2C) // $0460002C Domain 2 Page Size
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constant PI_BSD_DOM2_RLS($30) // $04600030..$04600033 PI: Domain 2 Release Register
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constant PI_BSD_DOM2_RLS($30) // $04600030 Domain 2 Release
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macro PI_WAIT() {
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macro PI_WAIT() {
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lui t5, PI_BASE
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lui t5, PI_BASE
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constant PIF_BASE($BFC0) // $1FC00000..$1FC007BF PIF Base Register
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constant PIF_BASE($BFC0) // $1FC00000..$1FC007BF PIF Base
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constant PIF_ROM($000) // $1FC00000..$1FC007BF PIF: Boot ROM
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constant PIF_ROM($000) // $1FC00000..$1FC007BF Boot ROM
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constant PIF_RAM($7C0) // $1FC007C0..$1FC007FF PIF: RAM (JoyChannel)
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constant PIF_RAM($7C0) // $1FC007C0..$1FC007FF RAM (JoyChannel)
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constant PIF_HWORD($7C4) // $1FC007C4..$1FC007C5 PIF: HWORD
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constant PIF_HWORD($7C4) // $1FC007C4..$1FC007C5 HWORD
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constant PIF_XBYTE($7C6) // $1FC007C6 PIF: Analog X Byte
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constant PIF_XBYTE($7C6) // $1FC007C6 PIF: Analog X Byte
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constant PIF_YBYTE($7C7) // $1FC007C7 PIF: Analog Y Byte
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constant PIF_YBYTE($7C7) // $1FC007C7 PIF: Analog Y Byte
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constant RI_BASE($A470) // $04700000..$0470001F RDRAM Interface (RI) Base Register
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constant RI_BASE($A470) // $04700000 RDRAM Interface (RI) Base
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constant RI_MODE($00) // $04700000..$04700003 RI: Mode Register
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constant RI_MODE($00) // $04700000 Mode
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constant RI_CONFIG($04) // $04700004..$04700007 RI: Config Register
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constant RI_CONFIG($04) // $04700004 Config
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constant RI_CURRENT_LOAD($08) // $04700008..$0470000B RI: Current Load Register
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constant RI_CURRENT_LOAD($08) // $04700008 Current Load
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constant RI_SELECT($0C) // $0470000C..$0470000F RI: Select Register
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constant RI_SELECT($0C) // $0470000C Select
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constant RI_REFRESH($10) // $04700010..$04700013 RI: Refresh Register
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constant RI_REFRESH($10) // $04700010 Refresh
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constant RI_LATENCY($14) // $04700014..$04700017 RI: Latency Register
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constant RI_LATENCY($14) // $04700014 Latency
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constant RI_RERROR($18) // $04700018..$0470001B RI: Read Error Register
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constant RI_RERROR($18) // $04700018 Read Error
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constant RI_WERROR($1C) // $0470001C..$0470001F RI: Write Error Register
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constant RI_WERROR($1C) // $0470001C Write Error
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constant SI_BASE($A480) // $04800000..$0480001B Serial Interface (SI) Base Register
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constant SI_BASE($A480) // $04800000 Serial Interface (SI) Base
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constant SI_DRAM_ADDR($00) // $04800000..$04800003 SI: DRAM Address Register
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constant SI_DRAM_ADDR($00) // $04800000 DRAM Address
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constant SI_PIF_ADDR_RD64B($04) // $04800004..$04800007 SI: Address Read 64B Register
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constant SI_PIF_ADDR_RD64B($04) // $04800004 Address Read 64B
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//*RESERVED*($08) // $04800008..$0480000B SI: Reserved Register
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//*RESERVED*($08) // $04800008 Reserved
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//*RESERVED*($0C) // $0480000C..$0480000F SI: Reserved Register
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//*RESERVED*($0C) // $0480000C Reserved
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constant SI_PIF_ADDR_WR64B($10) // $04800010..$04800013 SI: Address Write 64B Register
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constant SI_PIF_ADDR_WR64B($10) // $04800010 Address Write 64B
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//*RESERVED*($14) // $04800014..$04800017 SI: Reserved Register
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//*RESERVED*($14) // $04800014 Reserved
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constant SI_STATUS($18) // $04800018..$0480001B SI: Status Register
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constant SI_STATUS($18) // $04800018 Status
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macro SI_WAIT() {
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macro SI_WAIT() {
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lui a0, SI_BASE
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lui a0, SI_BASE
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constant SP_MEM_BASE($A400) // $04000000..$04000FFF SP MEM Base Register
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constant SP_MEM_BASE($A400) // $04000000 SP MEM Base Register
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constant SP_DMEM($0000) // $04000000..$04000FFF SP: RSP DMEM (4096 Bytes)
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constant SP_DMEM($0000) // $04000000 RSP DMEM (4096 Bytes)
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constant SP_IMEM($1000) // $04001000..$04001FFF SP: RSP IMEM (4096 Bytes)
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constant SP_IMEM($1000) // $04001000 RSP IMEM (4096 Bytes)
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constant SP_BASE($A404) // $04040000..$0404001F SP Base Register
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constant SP_BASE($A404) // $04040000 SP Base Register
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constant SP_MEM_ADDR($00) // $04040000..$04040003 SP: Master, SP Memory Address Register
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constant SP_MEM_ADDR($00) // $04040000 Master, SP Memory Address Register
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constant SP_DRAM_ADDR($04) // $04040004..$04040007 SP: Slave, SP DRAM DMA Address Register
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constant SP_DRAM_ADDR($04) // $04040004 Slave, SP DRAM DMA Address Register
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constant SP_RD_LEN($08) // $04040008..$0404000B SP: Read DMA Length Register
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constant SP_RD_LEN($08) // $04040008 Read DMA Length Register
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constant SP_WR_LEN($0C) // $0404000C..$0404000F SP: Write DMA Length Register
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constant SP_WR_LEN($0C) // $0404000C Write DMA Length Register
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constant SP_STATUS($10) // $04040010..$04040013 SP: Status Register
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constant SP_STATUS($10) // $04040010 Status Register
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constant SP_DMA_FULL($14) // $04040014..$04040017 SP: DMA Full Register
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constant SP_DMA_FULL($14) // $04040014 DMA Full Register
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constant SP_DMA_BUSY($18) // $04040018..$0404001B SP: DMA Busy Register
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constant SP_DMA_BUSY($18) // $04040018 DMA Busy Register
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constant SP_SEMAPHORE($1C) // $0404001C..$0404001F SP: Semaphore Register
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constant SP_SEMAPHORE($1C) // $0404001C Semaphore Register
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constant SP_PC_BASE($A408) // $04080000..$04080007 SP PC Base Register
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constant SP_PC_BASE($A408) // $04080000 SP PC Base Register
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constant SP_PC($00) // $04080000..$04080003 SP: PC Register
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constant SP_PC($00) // $04080000 PC Register
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constant SP_IBIST_REG($04) // $04080004..$04080007 SP: IMEM BIST Register
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constant SP_IBIST_REG($04) // $04080004 IMEM BIST Register
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// SP_STATUS Read Flags:
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// SP_STATUS Read Flags:
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constant SP_HALT($0001)
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constant SP_HALT($0001)
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constant SP_IO_FULL($0010)
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constant SP_IO_FULL($0010)
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constant SP_SINGLE_STEP($0020)
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constant SP_SINGLE_STEP($0020)
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constant SP_INT_ON_BREAK($0040) // Interrupt On Break
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constant SP_INT_ON_BREAK($0040) // Interrupt On Break
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constant SP_SG0($0080) // Signal 0 Set
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constant SP_SIG0($0080) // Signal 0 Set
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constant SP_SG1($0100) // Signal 1 Set
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constant SP_SIG1($0100) // Signal 1 Set
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constant SP_SG2($0200) // Signal 2 Set
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constant SP_SIG2($0200) // Signal 2 Set
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constant SP_SG3($0400) // Signal 3 Set
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constant SP_SIG3($0400) // Signal 3 Set
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constant SP_SG4($0800) // Signal 4 Set
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constant SP_SIG4($0800) // Signal 4 Set
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constant SP_SG5($1000) // Signal 5 Set
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constant SP_SIG5($1000) // Signal 5 Set
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constant SP_SG6($2000) // Signal 6 Set
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constant SP_SIG6($2000) // Signal 6 Set
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constant SP_SG7($4000) // Signal 7 Set
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constant SP_SIG7($4000) // Signal 7 Set
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// SP_STATUS Write Flags:
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// SP_STATUS Write Flags:
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constant SP_HALT_CLR($00000001)
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constant SP_HALT_CLR($00000001)
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constant SP_SINGLE_STEP_SET($00000040)
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constant SP_SINGLE_STEP_SET($00000040)
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constant SP_INT_ON_BREAK_CLR($00000080) // Clear Interrupt On Break
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constant SP_INT_ON_BREAK_CLR($00000080) // Clear Interrupt On Break
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constant SP_INT_ON_BREAK_SET($00000100) // Set Interrupt On Break
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constant SP_INT_ON_BREAK_SET($00000100) // Set Interrupt On Break
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constant SP_SG0_CLR($00000200) // Clear Signal 0
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constant SP_SIG0_CLR($00000200)
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constant SP_SG0_SET($00000400) // Set Signal 0
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constant SP_SIG0_SET($00000400)
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constant SP_SG1_CLR($00000800) // Clear Signal 1
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constant SP_SIG1_CLR($00000800)
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constant SP_SG1_SET($00001000) // Set Signal 1
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constant SP_SIG1_SET($00001000)
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constant SP_SG2_CLR($00002000) // Clear Signal 2
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constant SP_SIG2_CLR($00002000)
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constant SP_SG2_SET($00004000) // Set Signal 2
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constant SP_SIG2_SET($00004000)
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constant SP_SG3_CLR($00008000) // Clear Signal 3
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constant SP_SIG3_CLR($00008000)
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constant SP_SG3_SET($00010000) // Set Signal 3
|
constant SP_SIG3_SET($00010000)
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||||||
constant SP_SG4_CLR($00020000) // Clear Signal 4
|
constant SP_SIG4_CLR($00020000)
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constant SP_SG4_SET($00040000) // Set Signal 4
|
constant SP_SIG4_SET($00040000)
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constant SP_SG5_CLR($00080000) // Clear Signal 5
|
constant SP_SIG5_CLR($00080000)
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constant SP_SG5_SET($00100000) // Set Signal 5
|
constant SP_SIG5_SET($00100000)
|
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constant SP_SG6_CLR($00200000) // Clear Signal 6
|
constant SP_SIG6_CLR($00200000)
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||||||
constant SP_SG6_SET($00400000) // Set Signal 6
|
constant SP_SIG6_SET($00400000)
|
||||||
constant SP_SG7_CLR($00800000) // Clear Signal 7
|
constant SP_SIG7_CLR($00800000)
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||||||
constant SP_SG7_SET($01000000) // Set Signal 7
|
constant SP_SIG7_SET($01000000)
|
||||||
|
|
||||||
|
// signal conventions:
|
||||||
|
constant SP_YIELD(SP_SIG0)
|
||||||
|
constant SP_YIELDED(SP_SIG1)
|
||||||
|
constant SP_TASKDONE(SP_SIG2)
|
||||||
|
constant SP_RSPSIGNAL(SP_SIG3)
|
||||||
|
constant SP_CPUSIGNAL(SP_SIG4)
|
||||||
|
|
||||||
|
constant SP_YIELD_CLR(SP_SIG0_CLR)
|
||||||
|
constant SP_YIELD_SET(SP_SIG0_SET)
|
||||||
|
constant SP_YIELDED_CLR(SP_SIG1_CLR)
|
||||||
|
constant SP_YIELDED_SET(SP_SIG1_SET)
|
||||||
|
constant SP_TASKDONE_CLR(SP_SIG2_CLR)
|
||||||
|
constant SP_TASKDONE_SET(SP_SIG2_SET)
|
||||||
|
constant SP_RSPSIGNAL_CLR(SP_SIG3_CLR)
|
||||||
|
constant SP_RSPSIGNAL_SET(SP_SIG3_SET)
|
||||||
|
constant SP_CPUSIGNAL_CLR(SP_SIG4_CLR)
|
||||||
|
constant SP_CPUSIGNAL_SET(SP_SIG4_SET)
|
||||||
|
|
||||||
macro SP_DMA_WAIT() {
|
macro SP_DMA_WAIT() {
|
||||||
lui a0, SP_BASE
|
lui a0, SP_BASE
|
||||||
|
|
|
||||||
|
|
@ -435,11 +435,11 @@ K_MI_Loop:
|
||||||
K_MI_SP:
|
K_MI_SP:
|
||||||
KWriteString(KS_MI_SP)
|
KWriteString(KS_MI_SP)
|
||||||
|
|
||||||
lli t0, SP_SG3_CLR | SP_INT_CLR // delay slot
|
lli t0, SP_RSPSIGNAL_CLR | SP_INT_CLR
|
||||||
lui a1, SP_BASE
|
lui a1, SP_BASE
|
||||||
sw t0, SP_STATUS(a1)
|
sw t0, SP_STATUS(a1)
|
||||||
|
|
||||||
// then check andi t1, SP_SG1 | SP_SG2 ?
|
// then check andi t1, SP_YIELDED | SP_TASKDONE ?
|
||||||
|
|
||||||
lw t0, K_HISTORY(k0)
|
lw t0, K_HISTORY(k0)
|
||||||
ori t0, MI_INTR_SP
|
ori t0, MI_INTR_SP
|
||||||
|
|
|
||||||
2
main.asm
2
main.asm
|
|
@ -82,7 +82,7 @@ Start3D:
|
||||||
|
|
||||||
// prepare RSP
|
// prepare RSP
|
||||||
lui a0, SP_BASE
|
lui a0, SP_BASE
|
||||||
lli t0, SP_SG2_CLR | SP_SG1_CLR | SP_SG0_CLR | SP_INT_ON_BREAK_SET
|
lli t0, SP_INT_ON_BREAK_SET | SP_TASKDONE_CLR | SP_YIELDED_CLR | SP_YIELD_CLR
|
||||||
sw t0, SP_STATUS(a0)
|
sw t0, SP_STATUS(a0)
|
||||||
|
|
||||||
SP_HALT_WAIT()
|
SP_HALT_WAIT()
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue