261 lines
6.5 KiB
NASM
261 lines
6.5 KiB
NASM
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// not really a kernel,
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// just handling some low-level stuff like interrupts.
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Start:
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lui k0, K_BASE
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// copy our interrupt handlers into place.
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lui t0, 0x8000
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la t1, _InterruptStart
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la t2, _InterruptEnd
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-
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ld t3, 0(t1)
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ld t4, 8(t1)
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addiu t1, t1, 0x10
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ld t3, 0(t0)
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sd t4, 8(t0)
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addiu t0, t0, 0x10
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bne t1, t2,-
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cache 1, 0(t0) // not sure if this is necessary, but it doesn't hurt.
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// enable SI and PI interrupts.
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lui a0, PIF_BASE
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lli t0, 8
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sw t0, PIF_RAM+0x3C(a0)
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// SP defaults to RSP instruction memory: 0xA4001FF0
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// we can do better than that.
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lui sp, K_STACK_INIT_BASE
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// SP should always be 8-byte aligned
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// so that SD and LD instructions don't fail on it.
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subiu sp, sp, 8
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// TODO: just wipe a portion of RAM?
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sw r0, K_64DRIVE_MAGIC(k0)
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sw r0, K_REASON(k0)
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Drive64Init:
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lui gp, CI_BASE
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lui t2, 0x5544 // "UD" of "UDEV"
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lw t1, CI_HW_MAGIC(gp)
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ori t2, t2, 0x4556 // "EV" of "UDEV"
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beq t1, t2, Drive64Confirmed
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nop
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Drive64TryExtended:
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lui gp, CI_BASE_EXTENDED
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lw t1, CI_HW_MAGIC(gp)
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bne t1, t2, Drive64Done
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nop
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Drive64Confirmed:
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sw t2, K_64DRIVE_MAGIC(k0)
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sw gp, K_CI_BASE(k0)
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// enable writing to cartROM (SDRAM) for USB writing later
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lli t1, 0xF0
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CI_WAIT()
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sw t1, CI_COMMAND(gp) // send our command
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CI_WAIT()
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Drive64Done:
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// clear internal exception/interrupt value
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ori k1, r0, r0
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// load up most registers with a dummy value for debugging
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lui at, 0xCAFE
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ori at, r0, 0xBABE
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dsllv at, 32
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// attempting to use this as an address should trigger an interrupt
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ori at, r0, 0xDEAD
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dsllv at, 16
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ori at, r0, 0xBEEF
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// k0, k1, sp intentionally absent
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daddu v0, at, r0
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daddu v1, at, r0
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daddu a0, at, r0
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daddu a1, at, r0
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daddu a2, at, r0
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daddu a3, at, r0
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daddu t0, at, r0
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daddu t1, at, r0
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daddu t2, at, r0
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daddu t3, at, r0
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daddu t4, at, r0
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daddu t5, at, r0
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daddu t6, at, r0
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daddu t7, at, r0
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daddu s0, at, r0
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daddu s1, at, r0
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daddu s2, at, r0
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daddu s3, at, r0
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daddu s4, at, r0
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daddu s5, at, r0
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daddu s6, at, r0
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daddu s7, at, r0
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daddu t8, at, r0
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daddu t9, at, r0
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daddu gp, at, r0
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daddu fp, at, r0
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daddu ra, at, r0
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j Main
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nop
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align(0x10)
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_InterruptStart: // for copying purposes
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pushvar base
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// note that we jump to the handler by jr instead of j
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// because we want to change the PC to cached memory,
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// which depends on the higher bits that j cannot change.
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base 0x80000000
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InterruptTBLRefill:
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la k0, InterruptHandler
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jr k0
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lli k1, K_INT_TLB_REFILL
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nops(0x80000080)
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InterruptXTLBRefill:
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la k0, InterruptHandler
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jr k0
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lli k1, K_INT_XTLB_REFILL
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nops(0x80000100)
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InterruptCacheError: // A0000100?
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la k0, InterruptHandler
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jr k0
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lli k1, K_INT_CACHE_ERROR
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nops(0x80000180)
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InterruptOther:
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la k0, InterruptHandler
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jr k0
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lli k1, K_INT_OTHER
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nops(0x80000200)
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pullvar base
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_InterruptEnd: // for copying purposes
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InterruptHandler:
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lui k0, K_BASE
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sw k1, K_REASON(k0)
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sd at, K_DUMP+0x08(k0)
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// disable interrupts, clear exception and error level bits:
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mfc0 at, CP0_Status
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sw at, K_STATUS(k0) // TODO: restored later
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addiu at, r0, 0xFFFC
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and k1, k1, at
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mtc0 k1, CP0_Status
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mfc0 k1, CP0_Cause
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sw k1, K_CAUSE(k0)
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// TODO: option to only store clobbered registers
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// TODO: option to dump COP1 registers too
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sd r0, K_DUMP+0x00(k0) // intentional (it'd be weird if
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// r0 showed as nonzero in memory dumps)
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sd v0, K_DUMP+0x10(k0)
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sd v1, K_DUMP+0x18(k0)
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sd a0, K_DUMP+0x20(k0)
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sd a1, K_DUMP+0x28(k0)
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sd a2, K_DUMP+0x30(k0)
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sd a3, K_DUMP+0x38(k0)
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sd t0, K_DUMP+0x40(k0)
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sd t1, K_DUMP+0x48(k0)
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sd t2, K_DUMP+0x50(k0)
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sd t3, K_DUMP+0x58(k0)
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sd t4, K_DUMP+0x60(k0)
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sd t5, K_DUMP+0x68(k0)
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sd t6, K_DUMP+0x70(k0)
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sd t7, K_DUMP+0x78(k0)
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sd s0, K_DUMP+0x80(k0)
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sd s1, K_DUMP+0x88(k0)
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sd s2, K_DUMP+0x90(k0)
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sd s3, K_DUMP+0x98(k0)
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sd s4, K_DUMP+0xA0(k0)
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sd s5, K_DUMP+0xA8(k0)
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sd s6, K_DUMP+0xB0(k0)
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sd s7, K_DUMP+0xB8(k0)
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sd t8, K_DUMP+0xC0(k0)
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sd t9, K_DUMP+0xC8(k0)
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sd k0, K_DUMP+0xD0(k0)
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sd k1, K_DUMP+0xD8(k0)
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sd gp, K_DUMP+0xE0(k0)
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sd sp, K_DUMP+0xE8(k0)
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sd fp, K_DUMP+0xF0(k0)
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sd ra, K_DUMP+0xF8(k0)
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mfhi t0
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mflo t1
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sd t0, K_DUMP+0x100(k0)
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sd t1, K_DUMP+0x108(k0)
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// free to modify any GPR here
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lui k0, K_BASE
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ld t0, K_DUMP+0x100(k0)
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ld t1, K_DUMP+0x108(k0)
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mthi t0
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mtlo t1
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ld at, K_DUMP+0x08(k0)
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ld v0, K_DUMP+0x10(k0)
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ld v1, K_DUMP+0x18(k0)
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ld a0, K_DUMP+0x20(k0)
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ld a1, K_DUMP+0x28(k0)
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ld a2, K_DUMP+0x30(k0)
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ld a3, K_DUMP+0x38(k0)
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ld t0, K_DUMP+0x40(k0)
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ld t1, K_DUMP+0x48(k0)
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ld t2, K_DUMP+0x50(k0)
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ld t3, K_DUMP+0x58(k0)
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ld t4, K_DUMP+0x60(k0)
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ld t5, K_DUMP+0x68(k0)
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ld t6, K_DUMP+0x70(k0)
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ld t7, K_DUMP+0x78(k0)
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ld s0, K_DUMP+0x80(k0)
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ld s1, K_DUMP+0x88(k0)
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ld s2, K_DUMP+0x90(k0)
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ld s3, K_DUMP+0x98(k0)
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ld s4, K_DUMP+0xA0(k0)
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ld s5, K_DUMP+0xA8(k0)
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ld s6, K_DUMP+0xB0(k0)
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ld s7, K_DUMP+0xB8(k0)
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ld t8, K_DUMP+0xC0(k0)
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ld t9, K_DUMP+0xC8(k0)
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ld gp, K_DUMP+0xE0(k0)
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ld sp, K_DUMP+0xE8(k0)
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ld fp, K_DUMP+0xF0(k0)
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ld ra, K_DUMP+0xF8(k0)
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lw k1, K_CAUSE(k0)
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andi k1, k1, 0x2000 // check if this was a trap exception
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mfc0 k0, CP0_EPC
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beqz k1, ReturnFromInterrupt
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sw k0, K_EPC(k0)
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ReturnFromTrap:
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addiu k0, k0, 4
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ReturnFromInterrupt:
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// restore interrupts
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mfc0 k1, CP0_Status
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ori k1, k1, 1
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mtc0 k1, CP0_Status
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// wait, shouldn't this be ERET?
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rfe
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jr k0
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or k1, r0, r0
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nops((K_BASE << 16) + 0x10000)
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