mirror of
https://github.com/notwa/lips
synced 2024-05-06 03:13:22 -07:00
1151 lines
32 KiB
Lua
1151 lines
32 KiB
Lua
-- i've lost control of my life
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-- instructions: https://github.com/mikeryan/n64dev/tree/master/docs/n64ops
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-- CajeASM style assembly; refer to the manual included with CajeASM.
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-- lexer and parser are somewhat based on http://chunkbake.luaforge.net/
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local assembler = {
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_VERSION = 'assembler v1',
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_DESCRIPTION = 'Assembles MIPS assembly files for the R4300i CPU.',
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_URL = 'https://github.com/notwa/mm/blob/master/Lua/inject/assembler.lua',
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_LICENSE = [[
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Copyright (C) 2015 Connor Olding
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This program is licensed under the terms of the MIT License, and
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is distributed without any warranty. You should have received a
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copy of the license along with this program; see the file LICENSE.
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]],
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}
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local Class = function(inherit)
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local class = {}
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local mt_obj = {__index = class}
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local mt_class = {
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__call = function(self, ...)
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local obj = setmetatable({}, mt_obj)
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obj:init(...)
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return obj
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end,
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__index = inherit,
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}
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return setmetatable(class, mt_class)
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end
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-- TODO: maybe support reg# style too
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local registers = {
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[0]=
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'R0', 'AT', 'V0', 'V1', 'A0', 'A1', 'A2', 'A3',
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'T0', 'T1', 'T2', 'T3', 'T4', 'T5', 'T6', 'T7',
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'S0', 'S1', 'S2', 'S3', 'S4', 'S5', 'S6', 'S7',
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'T8', 'T9', 'K0', 'K1', 'GP', 'SP', 'S8', 'RA',
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}
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local fpu_registers = {
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[0]=
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'F0', 'F1', 'F2', 'F3', 'F4', 'F5', 'F6', 'F7',
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'F8', 'F9', 'F10', 'F11', 'F12', 'F13', 'F14', 'F15',
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'F16', 'F17', 'F18', 'F19', 'F20', 'F21', 'F22', 'F23',
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'F24', 'F25', 'F26', 'F27', 'F28', 'F29', 'F30', 'F31',
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}
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local all_instructions = {
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'ADD', 'ADDI', 'ADDIU', 'ADDU',
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'AND', 'ANDI',
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'BC1F', 'BC1FL',
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'BC1T', 'BC1TL',
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'BEQ', 'BEQL',
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'BGEZ', 'BGEZAL', 'BGEZALL', 'BGEZL',
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'BGTZ', 'BGTZL',
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'BLEZ', 'BLEZL',
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'BLTZ', 'BLTZAL', 'BLTZALL', 'BLTZL',
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'BNE', 'BNEL',
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'BREAK',
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'CACHE',
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'CFC1',
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'CTC1',
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'DADD', 'DADDI', 'DADDIU', 'DADDU',
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'DDIV', 'DDIVU',
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'DIV', 'DIVU',
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'DMFC1', 'DMTC1',
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'DMULT', 'DMULTU',
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'DSLL', 'DSLL32', 'DSLLV',
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'DSRA', 'DSRA32', 'DSRAV',
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'DSRL', 'DSRL32', 'DSRLV',
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'DSUB', 'DSUBU',
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'ERET',
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'J',
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'JAL', 'JALR',
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'JR',
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'LB', 'LBU',
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'LD',
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'LDC1', 'LDC2',
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'LDL', 'LDR',
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'LH',
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'LHU',
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'LL',
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'LLD',
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'LUI',
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'LW',
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'LWC1',
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'LWL', 'LWR',
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'LWU',
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'MFC0',
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'MFC1',
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'MFHI',
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'MFLO',
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'MTC0', 'MTC1',
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'MTHI', 'MTLO',
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'MULT', 'MULTU',
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'NOR',
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'OR', 'ORI',
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'SB',
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'SC',
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'SCD',
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'SD',
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'SDC1', 'SDC2',
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'SDL', 'SDR',
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'SH',
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'SLL', 'SLLV',
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'SLT', 'SLTI', 'SLTIU', 'SLTU',
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'SRA', 'SRAV',
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'SRL', 'SRLV',
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'SUB', 'SUBU',
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'SW',
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'SWC1',
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'SWL', 'SWR',
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'SYNC',
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'SYSCALL',
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'TEQ', 'TEQI',
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'TGE', 'TGEI', 'TGEIU', 'TGEU',
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'TLBP', 'TLBR', 'TLBWI', 'TLBWR',
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'TLT', 'TLTI', 'TLTIU', 'TLTU',
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'TNE', 'TNEI',
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'XOR', 'XORI',
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'ABS.D', 'ABS.S',
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'ADD.D', 'ADD.S',
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'CEIL.L.D', 'CEIL.L.S',
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'CEIL.W.D', 'CEIL.W.S',
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'CVT.D.L', 'CVT.D.S', 'CVT.D.W',
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'CVT.L.D', 'CVT.L.S',
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'CVT.S.D', 'CVT.S.L', 'CVT.S.W',
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'CVT.W.D', 'CVT.W.S',
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'DIV.D', 'DIV.S',
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'FLOOR.L.D', 'FLOOR.L.S',
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'FLOOR.W.D', 'FLOOR.W.S',
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'MOV.F', 'MOV.S',
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'MUL.F', 'MUL.S',
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'NEG.F', 'NEG.S',
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'ROUND.L.D', 'ROUND.L.S',
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'ROUND.W.D', 'ROUND.W.S',
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'SQRT.D', 'SQRT.S',
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'SUB.D', 'SUB.S',
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'TRUNC.L.S', 'TRUNC.W.D',
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'C.EQ.D', 'C.EQ.S',
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'C.F.D', 'C.F.S',
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'C.LE.D', 'C.LE.S',
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'C.LT.D', 'C.LT.S',
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'C.NGE.D', 'C.NGE.S',
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'C.NGL.D', 'C.NGL.S',
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'C.NGLE.D', 'C.NGLE.S',
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'C.NGT.D', 'C.NGT.S',
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'C.OLE.D', 'C.OLE.S',
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'C.OLT.D', 'C.OLT.S',
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'C.SEQ.D', 'C.SEQ.S',
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'C.SF.D', 'C.SF.S',
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'C.UEQ.D', 'C.UEQ.S',
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'C.ULE.D', 'C.ULE.S',
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'C.ULT.D', 'C.ULT.S',
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'C.UN.D', 'C.UN.S',
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-- pseudo-instructions
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'B',
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'BAL',
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'BEQI',
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'BNEI',
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'BGE', 'BGEI',
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'BLE', 'BLEI',
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'BLT', 'BLTI',
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'BGT', 'BGTI',
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'CL',
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'LI',
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'MOV',
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'NOP',
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'SUBI', 'SUBIU',
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}
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local all_directives = {
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'ALIGN', 'SKIP',
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'ASCII', 'ASCIIZ',
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'BYTE', 'HALFWORD', 'WORD', 'FLOAT',
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--'HEX', -- excluded here due to different syntax
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'INC', 'INCASM', 'INCLUDE',
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'INCBIN',
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'ORG',
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}
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local all_registers = {}
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for k, v in pairs(registers) do
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all_registers[k] = v
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end
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for k, v in pairs(fpu_registers) do
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all_registers[k + 32] = v
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end
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-- set up reverse table lookups
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local function revtable(t)
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for k, v in pairs(t) do
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t[v] = k
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end
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end
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revtable(registers)
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revtable(fpu_registers)
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revtable(all_registers)
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revtable(all_instructions)
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local argtypes = {
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bto = 'base rt offset',
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sti = 'rs rt immediate',
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std = 'rs rt rd', -- ending with 5 unset bits and a const
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st = 'rs rt', -- ending with 10 unset bits and a const
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tds = 'rs rd rs/sa', -- starting with 5 unset bits, ending with a const
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s = 'rs', -- followed by 15 unset bits and a const
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sto = 'rs rt offset',
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stc = 'rs rt code', -- followed by a const
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so = 'rs offset', -- with a const inbetween
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sync= 'stype', -- starting with 15 unset bits, ending with a const
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indx= 'index',
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lui = 'rt immediate', -- starting with 5 unset bits
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mf = 'rd', -- 10 unset bits on left, 5 on right, ending with a const
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jalr= 'rs rd', -- 5 unset bits inbetween, 5 on right, ending with a const
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code= 'code', -- ending with a const
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movf= 'rd fs', -- starting with const, ending with 11 unset bits
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bfo = 'base fs offset',
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tsdf= 'ft fs fd', -- starting with a const of 16, ending with a const
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tsdd= 'ft fs fd', -- starting with a const of 17, ending with a const
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}
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local at = argtypes -- temporary shorthand
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local instruction_handlers = {
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J = { 2, at.indx},
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JAL = { 3, at.indx},
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JALR = { 0, at.jalr, 9},
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MTHI = { 0, at.s, 17},
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MTLO = { 0, at.s, 19},
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JR = { 0, at.s, 8},
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BREAK = { 0, at.code,13},
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SYSCALL = { 0, at.code,12},
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SYNC = { 0, at.sync,15},
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--
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LB = {32, at.bto},
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LBU = {36, at.bto},
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LD = {55, at.bto},
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LDL = {26, at.bto},
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LDR = {27, at.bto},
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LH = {33, at.bto},
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LHU = {37, at.bto},
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LL = {48, at.bto},
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LLD = {52, at.bto},
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LW = {35, at.bto},
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LWL = {34, at.bto},
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LWR = {38, at.bto},
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LWU = {39, at.bto},
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SB = {40, at.bto},
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SC = {56, at.bto},
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SCD = {60, at.bto},
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SD = {63, at.bto},
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SDL = {44, at.bto},
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SDR = {45, at.bto},
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SH = {41, at.bto},
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SW = {43, at.bto},
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SWL = {42, at.bto},
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SWR = {46, at.bto},
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LUI = {15, at.lui},
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MFHI = { 0, at.mf, 16},
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MFLO = { 0, at.mf, 18},
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ADDI = { 8, at.sti},
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ADDIU = { 9, at.sti},
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ANDI = {12, at.sti},
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DADDI = {24, at.sti},
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DADDIU = {25, at.sti},
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ORI = {13, at.sti},
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SLTI = {10, at.sti},
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SLTIU = {11, at.sti},
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XORI = {14, at.sti},
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ADD = { 0, at.std, 32},
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ADDU = { 0, at.std, 33},
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AND = { 0, at.std, 36},
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DADD = { 0, at.std, 44},
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DADDU = { 0, at.std, 45},
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DSLLV = { 0, at.std, 20},
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DSUB = { 0, at.std, 46},
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DSUBU = { 0, at.std, 47},
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NOR = { 0, at.std, 39},
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OR = { 0, at.std, 37},
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SLLV = { 0, at.std, 4},
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SLT = { 0, at.std, 42},
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SLTU = { 0, at.std, 43},
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SRAV = { 0, at.std, 7},
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SRLV = { 0, at.std, 6},
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SUB = { 0, at.std, 34},
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SUBU = { 0, at.std, 35},
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XOR = { 0, at.std, 38},
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DDIV = { 0, at.st, 30},
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DDIVU = { 0, at.st, 31},
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DIV = { 0, at.st, 26},
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DIVU = { 0, at.st, 27},
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DMULT = { 0, at.st, 28},
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DMULTU = { 0, at.st, 29},
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MULT = { 0, at.st, 24},
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MULTU = { 0, at.st, 25},
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DSLL = { 0, at.tds, 56},
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DSLL32 = { 0, at.tds, 60},
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DSRA = { 0, at.tds, 59},
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DSRA32 = { 0, at.tds, 63},
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DSRAV = { 0, at.tds, 23},
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DSRL = { 0, at.tds, 58},
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DSRL32 = { 0, at.tds, 62},
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DSRLV = { 0, at.tds, 22},
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SLL = { 0, at.tds, 0},
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SRA = { 0, at.tds, 3},
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SRL = { 0, at.tds, 2},
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BEQ = { 4, at.sto},
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BEQL = {20, at.sto},
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BNE = { 5, at.sto},
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BNEL = {21, at.sto},
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BGEZ = { 1, at.so, 1},
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BGEZAL = { 1, at.so, 17},
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BGEZALL = { 1, at.so, 19},
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BGEZL = { 1, at.so, 3},
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BGTZ = { 7, at.so, 0},
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BGTZL = {23, at.so, 0},
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BLEZ = { 6, at.so, 0},
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BLEZL = {22, at.so, 0},
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BLTZ = { 1, at.so, 0},
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BLTZAL = { 1, at.so, 16},
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BLTZALL = { 1, at.so, 18},
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BLTZL = { 1, at.so, 2},
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TEQ = { 0, at.stc, 52},
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TGE = { 0, at.stc, 48},
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TGEU = { 0, at.stc, 49},
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TLT = { 0, at.stc, 50},
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TLTU = { 0, at.stc, 51},
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TNE = { 0, at.stc, 54},
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ADD_D = {17, at.tsdd, 0},
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ADD_S = {17, at.tsdf, 0},
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DIV_D = {17, at.tsdd, 3},
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DIV_S = {17, at.tsdf, 3},
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MUL_D = {17, at.tsdd, 2},
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MUL_S = {17, at.tsdf, 2},
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SUB_D = {17, at.tsdd, 1},
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SUB_S = {17, at.tsdf, 1},
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CFC1 = {17, at.movf, 2},
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CTC1 = {17, at.movf, 6},
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DMFC1 = {17, at.movf, 1},
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DMTC1 = {17, at.movf, 5},
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MFC0 = {16, at.movf, 0},
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MFC1 = {16, at.movf, 0},
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MTC0 = {17, at.movf, 4},
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MTC1 = {17, at.movf, 4},
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LDC1 = {53, at.bfo},
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LWC1 = {49, at.bfo},
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SDC1 = {61, at.bfo},
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SWC1 = {57, at.bfo},
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-- pseudo-instructions
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NOP = { 0, at.code, 0},
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}
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at = nil
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local Lexer = Class()
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function Lexer:init(asm)
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self.asm = asm
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self.pos = 1
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self.line = 1
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self.EOF = -1
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self:nextc()
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end
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local Dumper = Class()
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function Dumper:init(writer)
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self.writer = writer
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self.defines = {}
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self.labels = {}
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self.lines = {}
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end
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local Parser = Class()
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function Parser:init(writer)
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self.dumper = Dumper(writer)
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end
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function Lexer:error(msg)
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error(string.format('%s:%d: Error: %s', 'file.asm', self.line, msg), 2)
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end
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function Lexer:nextc()
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if self.pos > #self.asm then
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self.ord = self.EOF
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self.chr = ''
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self.chrchr = ''
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return
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end
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if self.chr == '\n' then
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self.line = self.line + 1
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end
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self.ord = string.byte(self.asm, self.pos)
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self.pos = self.pos + 1
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-- handle newlines; translate CRLF to LF
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if self.ord == 13 then
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if self.pos <= #self.asm and string.byte(self.asm, self.pos) == 10 then
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self.pos = self.pos + 1
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end
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self.ord = 10
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end
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self.chr = string.char(self.ord)
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if self.pos <= #self.asm then
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self.ord2 = string.byte(self.asm, self.pos)
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self.chr2 = string.char(self.ord2)
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self.chrchr = string.char(self.ord, self.ord2)
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else
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self.chrchr = self.chr
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end
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end
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function Lexer:skip_to_EOL()
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while self.chr ~= '\n' and self.ord ~= self.EOF do
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self:nextc()
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end
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end
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function Lexer:save_next()
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self.buff = self.buff..self.chr
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self:nextc()
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end
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function Lexer:read_chars(pattern)
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while string.find(self.chr, pattern) do
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self:save_next()
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end
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end
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function Lexer:read_number()
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self.buff = ''
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self:nextc()
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self:read_chars('%d')
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local num = tonumber(self.buff)
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if not num then self:error('invalid number') end
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return num
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end
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function Lexer:read_hex()
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self.buff = ''
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if self.chr ~= '$' then self:nextc() end
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self:nextc()
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self:read_chars('%x')
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local num = tonumber(self.buff, 16)
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if not num then self:error('invalid hex number') end
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return num
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end
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function Lexer:read_binary()
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self.buff = ''
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self:nextc()
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self:read_chars('[01]')
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local num = tonumber(self.buff, 2)
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if not num then self:error('invalid binary number') end
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return num
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|
end
|
|
|
|
function Lexer:skip_block_comment()
|
|
self:nextc()
|
|
self:nextc()
|
|
while true do
|
|
if self.ord == self.EOF then
|
|
self:error('incomplete block comment')
|
|
elseif self.chrchr == '*/' then
|
|
self:nextc()
|
|
self:nextc()
|
|
break
|
|
else
|
|
self:nextc()
|
|
end
|
|
end
|
|
end
|
|
|
|
function Lexer:lex()
|
|
while true do
|
|
if self.chr == '\n' then
|
|
self:nextc()
|
|
return 'EOL', '\n'
|
|
elseif self.ord == self.EOF then
|
|
return 'EOF', self.EOF
|
|
elseif self.chr == ';' then
|
|
self:skip_to_EOL()
|
|
elseif self.chrchr == '//' then
|
|
self:skip_to_EOL()
|
|
elseif self.chrchr == '/*' then
|
|
self:skip_block_comment()
|
|
elseif self.chr:find('%s') then
|
|
self:nextc()
|
|
elseif self.chr == '$' then
|
|
return 'NUM', self:read_hex()
|
|
elseif self.chr == '%' then
|
|
return 'NUM', self:read_binary()
|
|
elseif self.chr:find('%d') then
|
|
-- TODO: check if cajaasm accepts 0X0
|
|
if self.chr2 == 'x' or self.chr2 == 'X' then
|
|
return 'NUM', self:read_hex()
|
|
end
|
|
return 'NUM', self:read_number()
|
|
elseif self.chr == ',' then
|
|
self:nextc()
|
|
return 'SEP', ','
|
|
elseif self.chr == '[' then
|
|
self.buff = ''
|
|
self:nextc()
|
|
self:read_chars('[%w_]')
|
|
if self.chr ~= ']' then
|
|
self:error('invalid define name')
|
|
end
|
|
self:nextc()
|
|
if self.chr ~= ':' then
|
|
self:error('define requires a colon')
|
|
end
|
|
self:nextc()
|
|
return 'DEF', self.buff
|
|
elseif self.chr == '(' then
|
|
self.buff = ''
|
|
self:nextc()
|
|
self:read_chars('[%w_]')
|
|
if self.chr ~= ')' then
|
|
self:error('invalid register name')
|
|
end
|
|
self:nextc()
|
|
local up = self.buff:upper()
|
|
if not all_registers[up] then
|
|
self:error('not a register')
|
|
end
|
|
return 'DEREF', up
|
|
elseif self.chr == '.' then
|
|
self.buff = ''
|
|
self:read_chars('[%w]')
|
|
local up = self.buff:upper()
|
|
if not all_directives[up] then
|
|
self:error('not a directive')
|
|
end
|
|
if up == 'INC' or up == 'INCASM' or up == 'INCLUDE' then
|
|
return 'DIR', 'UP'
|
|
end
|
|
return 'DIR', up
|
|
elseif self.chr == '@' then
|
|
self.buff = ''
|
|
self:nextc()
|
|
self:read_chars('[%w_]')
|
|
return 'DEFSYM', self.buff
|
|
elseif self.chr:find('[%a_]') then
|
|
self.buff = ''
|
|
-- now that we know we're looking at an identifier,
|
|
-- we can start matching numbers and dots too.
|
|
self:read_chars('[%w_.]')
|
|
if self.chr == ':' then
|
|
if self.buff:find('%.') then
|
|
self:error('labels cannot contain dots')
|
|
end
|
|
self:nextc()
|
|
return 'LABEL', self.buff
|
|
end
|
|
local up = self.buff:upper()
|
|
if up == 'HEX' then
|
|
return 'DIR', up
|
|
elseif all_registers[up] then
|
|
return 'REG', up
|
|
elseif all_instructions[up] then
|
|
return 'INSTR', up:gsub('%.', '_')
|
|
else
|
|
if self.buff:find('%.') then
|
|
self:error('labels cannot contain dots')
|
|
end
|
|
return 'LABELSYM', self.buff
|
|
end
|
|
elseif self.chr == ']' then
|
|
self:error('unmatched closing bracket')
|
|
elseif self.chr == ')' then
|
|
self:error('unmatched closing parenthesis')
|
|
else
|
|
self:error('unknown character or control character')
|
|
end
|
|
end
|
|
end
|
|
|
|
function Parser:error(msg)
|
|
error(string.format('%s:%d: Error: %s', 'file.asm', self.line, msg), 2)
|
|
end
|
|
|
|
function Parser:advance()
|
|
self.tt, self.tok = self.lexer:lex()
|
|
self.line = self.lexer.line
|
|
return self.tt, self.tok
|
|
end
|
|
|
|
function Parser:is_EOL()
|
|
return self.tt == 'EOL' or self.tt == 'EOF'
|
|
end
|
|
|
|
function Parser:expect_EOL()
|
|
if self:is_EOL() then
|
|
self:advance()
|
|
return
|
|
end
|
|
self:error('expected end of line')
|
|
end
|
|
|
|
function Parser:optional_comma()
|
|
if self.tt == 'SEP' and self.tok == ',' then
|
|
self:advance()
|
|
return true
|
|
end
|
|
end
|
|
|
|
function Parser:number()
|
|
if self.tt ~= 'NUM' then
|
|
self:error('expected number')
|
|
end
|
|
local value = self.tok
|
|
self:advance()
|
|
return value
|
|
end
|
|
|
|
function Parser:directive()
|
|
local name = self.tok
|
|
self:advance()
|
|
if name == 'ORG' then
|
|
self.dumper:add_directive(name, self:number())
|
|
elseif name == 'ALIGN' or name == 'SKIP' then
|
|
local size = self:number()
|
|
if self:optional_comma() then
|
|
self.dumper:add_directive(name, size, self:number())
|
|
else
|
|
self.dumper:add_directive(name, size)
|
|
end
|
|
self:expect_EOL()
|
|
elseif name == 'BYTE' or name == 'HALFWORD' or name == 'WORD' then
|
|
self.dumper:add_directive(name, self:number())
|
|
while not self:is_EOL() do
|
|
self:advance()
|
|
self:optional_comma()
|
|
self.dumper:add_directive(name, self:number())
|
|
end
|
|
self:expect_EOL()
|
|
elseif name == 'HEX' then
|
|
self:error('unimplemented')
|
|
elseif name == 'INC' or name == 'INCBIN' then
|
|
self:error('unimplemented')
|
|
elseif name == 'FLOAT' or name == 'ASCII' or name == 'ASCIIZ' then
|
|
self:error('unimplemented')
|
|
else
|
|
self:error('unknown directive')
|
|
end
|
|
end
|
|
|
|
function Parser:register(t)
|
|
t = t or registers
|
|
if self.tt ~= 'REG' then
|
|
if self.tt == 'NUM' and self.tok == '0' then
|
|
-- i don't think cajeasm actually does this
|
|
self.tt = 'REG'
|
|
self.tok = 'R0'
|
|
else
|
|
self:error('expected register')
|
|
end
|
|
end
|
|
local reg = self.tok
|
|
if not t[reg] then
|
|
self:error('wrong type of register')
|
|
end
|
|
self:advance()
|
|
return reg
|
|
end
|
|
|
|
function Parser:deref()
|
|
if self.tt ~= 'DEREF' then
|
|
self:error('expected register to dereference')
|
|
end
|
|
local reg = self.tok
|
|
self:advance()
|
|
return reg
|
|
end
|
|
|
|
function Parser:const(relative)
|
|
if self.tt ~= 'NUM' and self.tt ~= 'DEFSYM' and self.tt ~= 'LABELSYM' then
|
|
self:error('expected constant')
|
|
end
|
|
if relative and self.tt == 'LABELSYM' then
|
|
self.tt = 'LABELREL'
|
|
end
|
|
local t = {self.tt, self.tok}
|
|
self:advance()
|
|
return t
|
|
end
|
|
|
|
function Parser:instruction()
|
|
local name = self.tok
|
|
self:advance()
|
|
local h = instruction_handlers[name]
|
|
|
|
if h == nil then
|
|
self:error('undefined instruction')
|
|
elseif h[2] == argtypes.bto then
|
|
-- OP rt, offset(base)
|
|
local rt = self:register()
|
|
self:optional_comma()
|
|
local offset = {'LOWER', self:const()}
|
|
local base = self:deref()
|
|
self.dumper:add_instruction_5_5_16(h[1], base, rt, offset)
|
|
elseif h[2] == argtypes.bfo then
|
|
-- OP ft, offset(base)
|
|
local ft = self:register(fpu_registers)
|
|
self:optional_comma()
|
|
local offset = {'LOWER', self:const()}
|
|
local base = self:deref()
|
|
self.dumper:add_instruction_5_5_16(h[1], base, ft, offset)
|
|
elseif h[2] == argtypes.sti then
|
|
-- OP rt, rs, immediate
|
|
local rt = self:register()
|
|
self:optional_comma()
|
|
local rs = self:register()
|
|
self:optional_comma()
|
|
local immediate = {'LOWER', self:const()}
|
|
self.dumper:add_instruction_5_5_16(h[1], rs, rt, immediate)
|
|
elseif h[2] == argtypes.std then
|
|
-- OP rd, rs, rt
|
|
local rd = self:register()
|
|
self:optional_comma()
|
|
local rs = self:register()
|
|
self:optional_comma()
|
|
local rt = self:register()
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_5_5_5_11(h[1], rs, rt, rd, const)
|
|
elseif h[2] == argtypes.st then
|
|
-- OP rs, rt
|
|
local rs = self:register()
|
|
self:optional_comma()
|
|
local rt = self:register()
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_5_5_16(h[1], rs, rt, const)
|
|
elseif h[2] == argtypes.tds then
|
|
local rd = self:register()
|
|
self:optional_comma()
|
|
local rt = self:register()
|
|
self:optional_comma()
|
|
local rs
|
|
if name == 'DSRAV' or name == 'DSRLV' then
|
|
-- OP rd, rt, rs
|
|
rs = self:register()
|
|
else
|
|
-- OP rd, rt, sa
|
|
rs = self:const()
|
|
end
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_5_5_5_5_6(h[1], 0, rt, rd, rs, const)
|
|
elseif h[2] == argtypes.s then
|
|
-- OP rs
|
|
local rs = self:register()
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_5_5_16(h[1], rs, 0, const)
|
|
elseif h[2] == argtypes.sto then
|
|
-- OP rs, rt, offset
|
|
local rs = self:register()
|
|
self:optional_comma()
|
|
local rt = self:register()
|
|
self:optional_comma()
|
|
local offset = self:const('relative')
|
|
self.dumper:add_instruction_5_5_16(h[1], rs, rt, offset)
|
|
elseif h[2] == argtypes.stc then
|
|
-- OP TEQ rs, rt
|
|
local rs = self:register()
|
|
self:optional_comma()
|
|
local rt = self:register()
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
-- FIXME: there's supposed to be 'code' before const
|
|
-- but i dunno what it's supposed to be
|
|
-- so i'm leaving it as zero here
|
|
self.dumper:add_instruction_5_5_16(h[1], rs, rt, const)
|
|
elseif h[2] == argtypes.so then
|
|
-- OP rs, offset
|
|
local rs = self:register()
|
|
self:optional_comma()
|
|
local offset = self:const('relative')
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_5_5_16(h[1], rs, const, offset)
|
|
elseif h[2] == argtypes.sync then
|
|
-- OP
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_26(h[1], const)
|
|
elseif h[2] == argtypes.indx then
|
|
-- OP target
|
|
local target = {'INDEX', self:const()}
|
|
self.dumper:add_instruction_26(h[1], target)
|
|
elseif h[2] == argtypes.lui then
|
|
-- OP rt, immediate
|
|
local rt = self:register()
|
|
self:optional_comma()
|
|
local immediate = {'UPPER', self:const()}
|
|
self.dumper:add_instruction_5_5_16(h[1], 0, rt, immediate)
|
|
elseif h[2] == argtypes.mf then
|
|
-- OP rd
|
|
local rd = self:register()
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_5_5_5_5_6(h[1], 0, 0, rd, 0, const)
|
|
elseif h[2] == argtypes.jalr then
|
|
-- OP rs, rd
|
|
local rs = self:register()
|
|
self:optional_comma()
|
|
local rd = self:register()
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_5_5_5_5_6(h[1], rs, 0, rd, 0, const)
|
|
local rd = self:register()
|
|
elseif h[2] == argtypes.code then
|
|
-- OP
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_26(h[1], const)
|
|
elseif h[2] == argtypes.movf then
|
|
local rt = self:register()
|
|
self:optional_comma()
|
|
local rd = nil
|
|
if name == 'MFC0' or name == 'MTC0' then
|
|
-- OP rt, rd
|
|
rd = self:register()
|
|
else
|
|
-- OP rt, fs
|
|
rd = self:register(fpu_registers)
|
|
end
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_5_5_5_5_6(h[1], const, rt, rd, 0, 0)
|
|
elseif h[2] == argtypes.tsdf then
|
|
-- OP fd, fs, ft
|
|
local fd = self:register(fpu_registers)
|
|
self:optional_comma()
|
|
local fs = self:register(fpu_registers)
|
|
self:optional_comma()
|
|
local ft = self:register(fpu_registers)
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_5_5_5_5_6(h[1], 16, ft, fs, fd, const)
|
|
elseif h[2] == argtypes.tsdd then
|
|
local fd = self:register(fpu_registers)
|
|
self:optional_comma()
|
|
local fs = self:register(fpu_registers)
|
|
self:optional_comma()
|
|
local ft = self:register(fpu_registers)
|
|
local const = h[3] or self:error('internal error: expected const')
|
|
self.dumper:add_instruction_5_5_5_5_6(h[1], 17, ft, fs, fd, const)
|
|
else
|
|
self:error('TODO')
|
|
end
|
|
self:expect_EOL()
|
|
end
|
|
|
|
function Parser:parse(asm)
|
|
self.asm = asm
|
|
self.lexer = Lexer(asm)
|
|
|
|
self:advance()
|
|
while self.tt ~= 'EOF' do
|
|
if self.tt == 'EOL' then
|
|
-- empty line
|
|
self:advance()
|
|
elseif self.tt == 'DEF' then
|
|
local name = self.tok
|
|
self:advance()
|
|
self.dumper:add_define(name, self:number())
|
|
elseif self.tt == 'DIR' then
|
|
self:directive()
|
|
elseif self.tt == 'LABEL' then
|
|
self.dumper:add_label(self.tok)
|
|
self:advance()
|
|
elseif self.tt == 'INSTR' then
|
|
self:instruction()
|
|
else
|
|
self:error('unexpected token (unknown instruction?)')
|
|
end
|
|
end
|
|
|
|
return self.dumper:dump()
|
|
end
|
|
|
|
function Dumper:error(msg)
|
|
-- TODO: sometimes internal error, sometimes not.
|
|
-- also, we should pass line numbers down to add_instruction.
|
|
error(string.format('Dumping Error: %s', msg), 2)
|
|
end
|
|
|
|
function Dumper:push(t)
|
|
--print(t.data)
|
|
table.insert(self.lines, t)
|
|
end
|
|
|
|
function Dumper:add_instruction_26(i, a)
|
|
local t = {}
|
|
t.sizes = {26}
|
|
t.data = {i, a}
|
|
self:push(t)
|
|
end
|
|
|
|
function Dumper:add_instruction_5_5_16(i, a, b, c)
|
|
local t = {}
|
|
t.sizes = {5, 5, 16}
|
|
t.data = {i, a, b, c}
|
|
self:push(t)
|
|
end
|
|
|
|
function Dumper:add_instruction_5_5_5_11(i, a, b, c, d)
|
|
local t = {}
|
|
t.sizes = {5, 5, 5, 11}
|
|
t.data = {i, a, b, c, d}
|
|
self:push(t)
|
|
end
|
|
|
|
function Dumper:add_instruction_5_5_5_5_6(i, a, b, c, d, e)
|
|
local t = {}
|
|
t.sizes = {5, 5, 5, 5, 6}
|
|
t.data = {i, a, b, c, d, e}
|
|
self:push(t)
|
|
end
|
|
|
|
function Dumper:add_define(name, number)
|
|
self.defines[name] = number
|
|
end
|
|
|
|
function Dumper:add_label(name)
|
|
self.labels[name] = #self.lines + 1
|
|
end
|
|
|
|
function Dumper:add_directive(...)
|
|
self:error('unimplemented directive')
|
|
end
|
|
|
|
function Dumper:print(uw, lw)
|
|
self.writer(('%04X%04X'):format(uw, lw))
|
|
end
|
|
|
|
function Dumper:desym(tok)
|
|
if type(tok[2]) == 'number' then
|
|
return tok[2]
|
|
elseif all_registers[tok] then
|
|
return registers[tok] or fpu_registers[tok]
|
|
elseif tok[1] == 'LABELSYM' then
|
|
--print('(label)', tok[2])
|
|
return self.labels[tok[2]]*4
|
|
elseif tok[1] == 'LABELREL' then
|
|
local rel = self.labels[tok[2]] - 2 - self.line
|
|
if rel > 0x8000 or rel <= -0x8000 then
|
|
self:error('branch too far')
|
|
end
|
|
return (0x10000 + rel) % 0x10000
|
|
elseif tok[1] == 'DEFSYM' then
|
|
--print('(define)')
|
|
local val = self.defines[tok[2]]
|
|
if val == nil then
|
|
self:error('unknown define')
|
|
end
|
|
return val
|
|
end
|
|
--print(tok)
|
|
self:error('failed to desym')
|
|
end
|
|
|
|
function Dumper:toval(tok)
|
|
if tok == nil then
|
|
self:error('nil value')
|
|
elseif type(tok) == 'number' then
|
|
return tok
|
|
elseif all_registers[tok] then
|
|
return registers[tok] or fpu_registers[tok]
|
|
end
|
|
if type(tok) == 'table' then
|
|
if #tok ~= 2 then
|
|
--print('toval', tok)
|
|
self:error('invalid token')
|
|
end
|
|
if tok[1] == 'UPPER' then
|
|
local val = self:desym(tok[2])
|
|
while val >= 0x10000 do
|
|
val = val/2
|
|
end
|
|
return val
|
|
elseif tok[1] == 'LOWER' then
|
|
local val = self:desym(tok[2]) % 0x10000
|
|
return val
|
|
elseif tok[1] == 'INDEX' then
|
|
local val
|
|
if type(tok[2]) == 'table' and tok[2][1] == 'LABELSYM' then
|
|
-- don't multiply by 4 twice
|
|
val = self:desym(tok[2])
|
|
else
|
|
val = self:desym(tok[2])*4
|
|
end
|
|
--print('(index)', val)
|
|
return val
|
|
else
|
|
return self:desym(tok)
|
|
end
|
|
end
|
|
--print('toval', tok)
|
|
self:error('invalid value')
|
|
end
|
|
|
|
function Dumper:validate(n, bits)
|
|
local max = 2^bits
|
|
if n == nil then
|
|
self:error('value is nil')
|
|
end
|
|
if n > max or n < 0 then
|
|
--print(('n %08X'):format(math.abs(n)))
|
|
self:error('value out of range')
|
|
end
|
|
end
|
|
|
|
function Dumper:valvar(tok, bits)
|
|
local val = self:toval(tok)
|
|
self:validate(val, bits)
|
|
return val
|
|
end
|
|
|
|
function Dumper:dump()
|
|
for i, t in ipairs(self.lines) do
|
|
self.line = i
|
|
local uw = 0
|
|
local lw = 0
|
|
local val = nil
|
|
|
|
local i = t.data[1]
|
|
uw = uw + i*0x400
|
|
|
|
if #t.sizes == 1 then
|
|
if t.sizes[1] == 26 then
|
|
val = self:valvar(t.data[2], 26)
|
|
uw = uw + math.floor(val/0x10000)
|
|
lw = lw + val % 0x10000
|
|
else
|
|
self:error('bad 1-size')
|
|
end
|
|
elseif #t.sizes == 3 then
|
|
if t.sizes[1] == 5 and t.sizes[2] == 5 and t.sizes[3] == 16 then
|
|
val = self:valvar(t.data[2], 5)
|
|
uw = uw + val*0x20
|
|
val = self:valvar(t.data[3], 5)
|
|
uw = uw + val
|
|
val = self:valvar(t.data[4], 16)
|
|
lw = lw + val
|
|
else
|
|
self:error('bad 3-size')
|
|
end
|
|
elseif #t.sizes == 4 then
|
|
if t.sizes[1] == 5 and t.sizes[2] == 5 and t.sizes[3] == 5 and t.sizes[4] == 11 then
|
|
val = self:valvar(t.data[2], 5)
|
|
uw = uw + val*0x20
|
|
val = self:valvar(t.data[3], 5)
|
|
uw = uw + val
|
|
val = self:valvar(t.data[4], 5)
|
|
lw = lw + val*0x800
|
|
val = self:valvar(t.data[5], 11)
|
|
lw = lw + val
|
|
else
|
|
self:error('bad 4-size')
|
|
end
|
|
elseif #t.sizes == 5 then
|
|
if t.sizes[1] == 5 and t.sizes[2] == 5 and t.sizes[3] == 5 and t.sizes[4] == 5 and t.sizes[5] == 6 then
|
|
val = self:valvar(t.data[2], 5)
|
|
uw = uw + val*0x20
|
|
val = self:valvar(t.data[3], 5)
|
|
uw = uw + val
|
|
val = self:valvar(t.data[4], 5)
|
|
lw = lw + val*0x800
|
|
val = self:valvar(t.data[5], 5)
|
|
lw = lw + val*0x40
|
|
val = self:valvar(t.data[6], 6)
|
|
lw = lw + val
|
|
else
|
|
self:error('bad 5-size')
|
|
end
|
|
else
|
|
self:error('unknown n-size')
|
|
end
|
|
|
|
self:print(uw, lw)
|
|
end
|
|
end
|
|
|
|
local function assemble(fn_or_asm, writer)
|
|
-- assemble a MIPS R4300i assembly file
|
|
-- if fn_or_asm contains a newline; treat as assembly, otherwise load file
|
|
-- returns error message on error, or nil on success
|
|
fn_or_asm = tostring(fn_or_asm)
|
|
writer = writer or io.write
|
|
|
|
function main()
|
|
local asm = ''
|
|
if fn_or_asm:find('[\r\n]') then
|
|
asm = fn_or_asm
|
|
else
|
|
local f = io.open(fn_or_asm, 'r')
|
|
if not f then
|
|
error('could not read assembly file', 1)
|
|
end
|
|
asm = f:read('*a')
|
|
f:close()
|
|
end
|
|
|
|
local parser = Parser(writer)
|
|
return parser:parse(asm)
|
|
end
|
|
|
|
local ok, err = pcall(main)
|
|
return err
|
|
end
|
|
|
|
return setmetatable(assembler, {
|
|
__call = function(_, ...)
|
|
return assemble(...)
|
|
end,
|
|
|
|
Lexer = Lexer,
|
|
Parser = Parser,
|
|
Dumper = Dumper,
|
|
|
|
registers = registers,
|
|
fpu_registers = fpu_registers,
|
|
all_registers = all_registers,
|
|
all_instructions = all_instructions,
|
|
all_directives = all_directives,
|
|
argtypes = argtypes,
|
|
})
|