mirror of
https://github.com/notwa/lips
synced 2025-03-09 03:32:49 -07:00
a bit of refactoring and cleanup
update copyright use more locals store an empty table (__) to save memory reorder instructions table add a few comments
This commit is contained in:
parent
f630990c6e
commit
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2 changed files with 86 additions and 71 deletions
2
LICENSE
2
LICENSE
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@ -1,4 +1,4 @@
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Copyright (C) 2015 Connor Olding
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Copyright (C) 2015,2016 Connor Olding
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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155
lips.lua
155
lips.lua
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@ -4,7 +4,7 @@ local assembler = {
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_DESCRIPTION = 'Assembles MIPS assembly files for the R4300i CPU.',
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_URL = 'https://github.com/notwa/lips/',
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_LICENSE = [[
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Copyright (C) 2015 Connor Olding
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Copyright (C) 2015,2016 Connor Olding
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This program is licensed under the terms of the MIT License, and
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is distributed without any warranty. You should have received a
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@ -12,14 +12,26 @@ local assembler = {
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]],
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}
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local __ = {}
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local byte = string.byte
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local char = string.char
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local coroutine = coroutine
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local error = error
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local find = string.find
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local format = string.format
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local floor = math.floor
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local format = string.format
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local insert = table.insert
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local ipairs = ipairs
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local open = io.open
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local pairs = pairs
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local pcall = pcall
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local print = print
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local setmetatable = setmetatable
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local tonumber = tonumber
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local tostring = tostring
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local type = type
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local Class = function(inherit)
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local function Class(inherit)
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local class = {}
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local mt_obj = {__index = class}
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local mt_class = {
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@ -39,7 +51,7 @@ local function bitrange(x, lower, upper)
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end
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local function readfile(fn)
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local f = io.open(fn, 'r')
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local f = open(fn, 'r')
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if not f then
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error('could not open assembly file for reading: '..tostring(fn), 2)
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end
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@ -110,6 +122,7 @@ revtable(fpu_registers)
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revtable(all_registers)
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revtable(all_directives)
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-- alternate register names
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registers['ZERO'] = 0
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all_registers['ZERO'] = 0
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registers['S8'] = 30
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@ -178,8 +191,6 @@ local instructions = {
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JALR = {0, 'ds', 's0d0C', 9},
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MTHI = {0, 's', 's000C', 17},
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MTLO = {0, 's', 's000C', 19},
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JR = {0, 's', 's000C', 8},
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BREAK = {0, '', '0000C', 13},
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@ -216,6 +227,9 @@ local instructions = {
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MFHI = {0, 'd', '00d0C', 16},
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MFLO = {0, 'd', '00d0C', 18},
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MTHI = {0, 's', 's000C', 17},
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MTLO = {0, 's', 's000C', 19},
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ADDI = { 8, 'tsK', 'sti'},
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ADDIU = { 9, 'tsK', 'sti'},
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ANDI = {12, 'tsK', 'sti'},
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@ -284,6 +298,8 @@ local instructions = {
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BLTZALL = { 1, 'sr', 'sCo', 18},
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BLTZL = { 1, 'sr', 'sCo', 2},
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-- coprocessor-related instructions
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TEQ = {0, 'st', 'st00C', 52},
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TGE = {0, 'st', 'st00C', 48},
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TGEU = {0, 'st', 'st00C', 49},
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@ -291,14 +307,12 @@ local instructions = {
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TLTU = {0, 'st', 'st00C', 51},
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TNE = {0, 'st', 'st00C', 54},
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ADD_D = {17, 'DST', 'FTSDC', 0, fmt_double},
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ADD_S = {17, 'DST', 'FTSDC', 0, fmt_single},
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DIV_D = {17, 'DST', 'FTSDC', 3, fmt_double},
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DIV_S = {17, 'DST', 'FTSDC', 3, fmt_single},
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MUL_D = {17, 'DST', 'FTSDC', 2, fmt_double},
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MUL_S = {17, 'DST', 'FTSDC', 2, fmt_single},
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SUB_D = {17, 'DST', 'FTSDC', 1, fmt_double},
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SUB_S = {17, 'DST', 'FTSDC', 1, fmt_single},
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TEQI = {1, 'si', 'sCi', 12},
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TGEI = {1, 'si', 'sCi', 8},
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TGEIU = {1, 'si', 'sCi', 9},
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TLTI = {1, 'si', 'sCi', 10},
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TLTIU = {1, 'si', 'sCi', 11},
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TNEI = {1, 'si', 'sCi', 14},
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CFC1 = {17, 'tS', 'CtS00', 2},
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CTC1 = {17, 'tS', 'CtS00', 6},
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@ -314,6 +328,31 @@ local instructions = {
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SDC1 = {61, 'Tob', 'bTo'},
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SWC1 = {57, 'Tob', 'bTo'},
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-- immediate limited to 3 bits?
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CACHE = {47, 'iob', 'bio'},
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-- misuses 'F' to write the initial bit
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ERET = {16, '', 'F000C', 24, 16},
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TLBP = {16, '', 'F000C', 8, 16},
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TLBR = {16, '', 'F000C', 1, 16},
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TLBWI = {16, '', 'F000C', 2, 16},
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TLBWR = {16, '', 'F000C', 6, 16},
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-- only one condition code on the R4300i?
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BC1F = {17, 'r', 'FCo', 0, 8},
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BC1FL = {17, 'r', 'FCo', 2, 8},
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BC1T = {17, 'r', 'FCo', 1, 8},
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BC1TL = {17, 'r', 'FCo', 3, 8},
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ADD_D = {17, 'DST', 'FTSDC', 0, fmt_double},
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ADD_S = {17, 'DST', 'FTSDC', 0, fmt_single},
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DIV_D = {17, 'DST', 'FTSDC', 3, fmt_double},
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DIV_S = {17, 'DST', 'FTSDC', 3, fmt_single},
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MUL_D = {17, 'DST', 'FTSDC', 2, fmt_double},
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MUL_S = {17, 'DST', 'FTSDC', 2, fmt_single},
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SUB_D = {17, 'DST', 'FTSDC', 1, fmt_double},
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SUB_S = {17, 'DST', 'FTSDC', 1, fmt_single},
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C_EQ_D = {17, 'ST', 'FTS0C', 50, fmt_double},
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C_EQ_S = {17, 'ST', 'FTS0C', 50, fmt_single},
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C_F_D = {17, 'ST', 'FTS0C', 48, fmt_double},
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@ -383,30 +422,8 @@ local instructions = {
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TRUNC_W_D={17, 'DS', 'F0SDC', 13, fmt_double},
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TRUNC_W_S={17, 'DS', 'F0SDC', 13, fmt_double},
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TEQI = {1, 'si', 'sCi', 12},
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TGEI = {1, 'si', 'sCi', 8},
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TGEIU = {1, 'si', 'sCi', 9},
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TLTI = {1, 'si', 'sCi', 10},
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TLTIU = {1, 'si', 'sCi', 11},
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TNEI = {1, 'si', 'sCi', 14},
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-- immediate limited to 3 bits?
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CACHE = {47, 'iob', 'bio'},
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-- misuses 'F' to write the initial bit
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ERET = {16, '', 'F000C', 24, 16},
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TLBP = {16, '', 'F000C', 8, 16},
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TLBR = {16, '', 'F000C', 1, 16},
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TLBWI = {16, '', 'F000C', 2, 16},
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TLBWR = {16, '', 'F000C', 6, 16},
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-- only one condition code on the R4300i?
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BC1F = {17, 'r', 'FCo', 0, 8},
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BC1FL = {17, 'r', 'FCo', 2, 8},
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BC1T = {17, 'r', 'FCo', 1, 8},
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BC1TL = {17, 'r', 'FCo', 3, 8},
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-- pseudo-instructions
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B = {4, 'r', '00o'}, -- BEQ R0, R0, offset
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BAL = {1, 'r', '0Co', 17}, -- BGEZAL R0, offset
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BEQZ = {4, 'sr', 's0o'}, -- BEQ RS, R0, offset
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@ -420,37 +437,37 @@ local instructions = {
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SUBIU = {9, 'tsk', 'sti'}, -- ADDIU RT, RS, -immediate
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-- ...that expand to multiple instructions
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LI = {}, -- only one instruction for values < 0x10000
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LA = {},
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LI = __, -- only one instruction for values < 0x10000
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LA = __,
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-- variable arguments
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PUSH = {},
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POP = {},
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JPOP = {},
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PUSH = __,
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POP = __,
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JPOP = __,
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ABS = {}, -- BGEZ NOP SUBU?
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MUL = {}, -- MULT MFLO
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--DIV = {}, -- 3 arguments
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REM = {}, -- 3 arguments
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ABS = __, -- BGEZ NOP SUBU?
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MUL = __, -- MULT MFLO
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--DIV = __, -- 3 arguments
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REM = __, -- 3 arguments
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NAND = {}, -- AND, NOT
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NANDI = {}, -- ANDI, NOT
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NORI = {}, -- ORI, NOT
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ROL = {}, -- SLL, SRL, OR
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ROR = {}, -- SRL, SLL, OR
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NAND = __, -- AND, NOT
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NANDI = __, -- ANDI, NOT
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NORI = __, -- ORI, NOT
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ROL = __, -- SLL, SRL, OR
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ROR = __, -- SRL, SLL, OR
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SEQ = {}, SEQI = {}, SEQIU = {}, SEQU = {},
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SGE = {}, SGEI = {}, SGEIU = {}, SGEU = {},
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SGT = {}, SGTI = {}, SGTIU = {}, SGTU = {},
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SLE = {}, SLEI = {}, SLEIU = {}, SLEU = {},
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SNE = {}, SNEI = {}, SNEIU = {}, SNEU = {},
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SEQ = __, SEQI = __, SEQIU = __, SEQU = __,
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SGE = __, SGEI = __, SGEIU = __, SGEU = __,
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SGT = __, SGTI = __, SGTIU = __, SGTU = __,
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SLE = __, SLEI = __, SLEIU = __, SLEU = __,
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SNE = __, SNEI = __, SNEIU = __, SNEU = __,
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BEQI = {},
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BNEI = {},
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BGE = {}, BGEI = {},
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BLE = {}, BLEI = {},
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BLT = {}, BLTI = {},
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BGT = {}, BGTI = {},
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BEQI = __,
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BNEI = __,
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BGE = __, BGEI = __,
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BLE = __, BLEI = __,
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BLT = __, BLTI = __,
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BGT = __, BGTI = __,
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}
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local all_instructions = {}
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@ -1550,9 +1567,8 @@ function Dumper:add_label(name)
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end
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function Dumper:add_bytes(line, ...)
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local bs = {...}
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local t
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local use_last = self.lastcommand and self.lastcommand.kind == 'bytes'
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local t
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if use_last then
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t = self.lastcommand
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else
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@ -1561,7 +1577,7 @@ function Dumper:add_bytes(line, ...)
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t.size = 0
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end
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t.line = line
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for _, b in ipairs(bs) do
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for _, b in ipairs{...} do
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t.size = t.size + 1
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t[t.size] = b
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end
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@ -1639,7 +1655,7 @@ function Dumper:desym(tok)
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end
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return rel % 0x10000
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end
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self:error('failed to desym')
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self:error('failed to desym') -- internal error?
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end
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function Dumper:toval(tok)
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@ -1689,13 +1705,13 @@ function Dumper:toval(tok)
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return self:desym(tok)
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end
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end
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self:error('invalid value')
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self:error('invalid value') -- internal error?
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end
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function Dumper:validate(n, bits)
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local max = 2^bits
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if n == nil then
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self:error('value is nil')
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self:error('value is nil') -- internal error?
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end
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if n > max or n < 0 then
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self:error('value out of range')
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@ -1785,8 +1801,7 @@ function assembler.word_writer()
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if pos > max then
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max = pos
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end
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else
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if max == -1 then return end
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elseif max >= 0 then
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for i=0, max, 4 do
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local a = buff[i+0] or '00'
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local b = buff[i+1] or '00'
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