add a really basic test

statements
Connor Olding 7 years ago
parent 0678d3eb58
commit 9192a655f7

@ -0,0 +1,230 @@
J 0x80000000
JAL 0x80000000
JALR r0, r0
JR r0
BREAK
SYSCALL
SYNC
LB r0, 0(r0)
LBU r0, 0(r0)
LD r0, 0(r0)
LDL r0, 0(r0)
LDR r0, 0(r0)
LH r0, 0(r0)
LHU r0, 0(r0)
LL r0, 0(r0)
LLD r0, 0(r0)
LW r0, 0(r0)
LWL r0, 0(r0)
LWR r0, 0(r0)
LWU r0, 0(r0)
SB r0, 0(r0)
SC r0, 0(r0)
SCD r0, 0(r0)
SD r0, 0(r0)
SDL r0, 0(r0)
SDR r0, 0(r0)
SH r0, 0(r0)
SW r0, 0(r0)
SWL r0, 0(r0)
SWR r0, 0(r0)
LUI r0, 0
MFHI r0
MFLO r0
MTHI r0
MTLO r0
ADDI r0, r0, 0
ADDIU r0, r0, 0
ANDI r0, r0, 0
DADDI r0, r0, 0
DADDIU r0, r0, 0
ORI r0, r0, 0
SLTI r0, r0, 0
SLTIU r0, r0, 0
XORI r0, r0, 0
ADD r0, r0, r0
ADDU r0, r0, r0
AND r0, r0, r0
DADD r0, r0, r0
DADDU r0, r0, r0
DSLLV r0, r0, r0
DSUB r0, r0, r0
DSUBU r0, r0, r0
NOR r0, r0, r0
OR r0, r0, r0
SLLV r0, r0, r0
SLT r0, r0, r0
SLTU r0, r0, r0
SRAV r0, r0, r0
SRLV r0, r0, r0
SUB r0, r0, r0
SUBU r0, r0, r0
XOR r0, r0, r0
DDIV r0, r0
DDIVU r0, r0
DIV r0, r0
DIVU r0, r0
DMULT r0, r0
DMULTU r0, r0
MULT r0, r0
MULTU r0, r0
DSLL r0, r0, 0
DSLL32 r0, r0, 0
DSRA r0, r0, 0
DSRA32 r0, r0, 0
DSRAV r0, r0, r0
DSRL r0, r0, 0
DSRL32 r0, r0, 0
DSRLV r0, r0, r0
SLL r0, r0, 0
SRA r0, r0, 0
SRL r0, r0, 0
BEQ r0, r0, 0x80000000
BEQL r0, r0, 0x80000000
BNE r0, r0, 0x80000000
BNEL r0, r0, 0x80000000
BGEZ r0, 0x80000000
BGEZAL r0, 0x80000000
BGEZALL r0, 0x80000000
BGEZL r0, 0x80000000
BGTZ r0, 0x80000000
BGTZL r0, 0x80000000
BLEZ r0, 0x80000000
BLEZL r0, 0x80000000
BLTZ r0, 0x80000000
BLTZAL r0, 0x80000000
BLTZALL r0, 0x80000000
BLTZL r0, 0x80000000
TEQ r0, r0
TGE r0, r0
TGEU r0, r0
TLT r0, r0
TLTU r0, r0
TNE r0, r0
TEQI r0, 0
TGEI r0, 0
TGEIU r0, 0
TLTI r0, 0
TLTIU r0, 0
TNEI r0, 0
CFC1 r0, f0
CTC1 r0, f0
DMFC1 r0, f0
DMTC1 r0, f0
MFC0 r0, Index
MFC1 r0, f0
MTC0 r0, Index
MTC1 r0, f0
LDC1 f0, 0(r0)
LWC1 f0, 0(r0)
SDC1 f0, 0(r0)
SWC1 f0, 0(r0)
CACHE 0, 0(r0)
ERET
TLBP
TLBR
TLBWI
TLBWR
BC1F 0x80000000
BC1FL 0x80000000
BC1T 0x80000000
BC1TL 0x80000000
ADD.D f0, f0, f0
ADD.S f0, f0, f0
DIV.D f0, f0, f0
DIV.S f0, f0, f0
MUL.D f0, f0, f0
MUL.S f0, f0, f0
SUB.D f0, f0, f0
SUB.S f0, f0, f0
C.EQ.D f0, f0
C.EQ.S f0, f0
C.F.D f0, f0
C.F.S f0, f0
C.LE.D f0, f0
C.LE.S f0, f0
C.LT.D f0, f0
C.LT.S f0, f0
C.NGE.D f0, f0
C.NGE.S f0, f0
C.NGL.D f0, f0
C.NGL.S f0, f0
C.NGLE.D f0, f0
C.NGLE.S f0, f0
C.NGT.D f0, f0
C.NGT.S f0, f0
C.OLE.D f0, f0
C.OLE.S f0, f0
C.OLT.D f0, f0
C.OLT.S f0, f0
C.SEQ.D f0, f0
C.SEQ.S f0, f0
C.SF.D f0, f0
C.SF.S f0, f0
C.UEQ.D f0, f0
C.UEQ.S f0, f0
C.ULE.D f0, f0
C.ULE.S f0, f0
C.ULT.D f0, f0
C.ULT.S f0, f0
C.UN.D f0, f0
C.UN.S f0, f0
CVT.D.L f0, f0
CVT.D.S f0, f0
CVT.D.W f0, f0
CVT.L.D f0, f0
CVT.L.S f0, f0
CVT.S.D f0, f0
CVT.S.L f0, f0
CVT.S.W f0, f0
CVT.W.D f0, f0
CVT.W.S f0, f0
ABS.D f0, f0
ABS.S f0, f0
CEIL.L.D f0, f0
CEIL.L.S f0, f0
CEIL.W.D f0, f0
CEIL.W.S f0, f0
FLOOR.L.D f0, f0
FLOOR.L.S f0, f0
FLOOR.W.D f0, f0
FLOOR.W.S f0, f0
MOV.D f0, f0
MOV.S f0, f0
NEG.D f0, f0
NEG.S f0, f0
ROUND.L.D f0, f0
ROUND.L.S f0, f0
ROUND.W.D f0, f0
ROUND.W.S f0, f0
SQRT.D f0, f0
SQRT.S f0, f0
TRUNC.L.D f0, f0
TRUNC.L.S f0, f0
TRUNC.W.D f0, f0
TRUNC.W.S f0, f0

@ -0,0 +1,206 @@
@00000000
08000000
0C000000
00000009
00000008
0000000D
0000000C
0000000F
80000000
90000000
DC000000
68000000
6C000000
84000000
94000000
C0000000
D0000000
8C000000
88000000
98000000
9C000000
A0000000
E0000000
F0000000
FC000000
B0000000
B4000000
A4000000
AC000000
A8000000
B8000000
3C000000
00000010
00000012
00000011
00000013
20000000
24000000
30000000
60000000
64000000
34000000
28000000
2C000000
38000000
00000020
00000021
00000024
0000002C
0000002D
00000014
0000002E
0000002F
00000027
00000025
00000004
0000002A
0000002B
00000007
00000006
00000022
00000023
00000026
0000001E
0000001F
0000001A
0000001B
0000001C
0000001D
00000018
00000019
00000038
0000003C
0000003B
0000003F
00000017
0000003A
0000003E
00000016
00000000
00000003
00000002
1000FFAE
5000FFAD
1400FFAC
5400FFAB
0401FFAA
0411FFA9
0413FFA8
0403FFA7
1C00FFA6
5C00FFA5
1800FFA4
5800FFA3
0400FFA2
0410FFA1
0412FFA0
0402FF9F
00000034
00000030
00000031
00000032
00000033
00000036
040C0000
04080000
04090000
040A0000
040B0000
040E0000
44400000
44C00000
44200000
44A00000
40000000
44000000
40800000
44800000
D4000000
C4000000
F4000000
E4000000
BC000000
42000018
42000008
42000001
42000002
42000006
4500FF80
4502FF7F
4501FF7E
4503FF7D
46200000
46000000
46200003
46000003
46200002
46000002
46200001
46000001
46200032
46000032
46200030
46000030
4620003E
4600003E
4620003C
4600003C
4620003D
4600003D
4620003B
4600003B
46200039
46000039
4620003F
4600003F
46200036
46000036
46200034
46000034
4620003A
4600003A
46200038
46000038
46200033
46000033
46200037
46000037
46200035
46000035
46200031
46000031
46A00021
46000021
46800021
46200025
46000025
46200020
46A00020
46800020
46200024
46000024
46200005
46000005
4620000A
4600000A
4620000E
4600000E
4620000B
4600000B
4620000F
4600000F
46200006
46000006
46200007
46000007
46200008
46000008
4620000C
4600000C
46200004
46000004
46200009
46000009
4620000D
4600000D

@ -0,0 +1,54 @@
describe("lips", function()
setup(function()
--local globalize = require "strict" -- FIXME
local function globalize(t)
for k, v in pairs(t) do
_G[k] = v
end
end
local lips = require "lips.init"
local dummy = function() end
local lipstick = function(fn, options)
options = options or {}
options.unsafe = true
local writer = lips.writers.make_tester()
lips(fn, writer, options)
return writer()
end
local function simple_read(fn)
local f = io.open(fn, 'r')
if f == nil then
error("couldn't open file for reading: "..tostring(fn), 2)
end
local data = f:read("*a")
f:close()
return data
end
local function simple_test(name)
local expected = simple_read("spec/"..name..".txt")
local ret = lipstick("spec/"..name..".asm")
assert.is_equal(expected, ret)
end
globalize{
lips = lips,
dummy = dummy,
lipstick = lipstick,
simple_read = simple_read,
simple_test = simple_test,
}
end)
it("assembles all basic CPU instructions", function()
-- no pseudo stuff, just plain MIPS
simple_test("basic")
end)
it("assembles all registers", function()
pending("all registers including aliases and coprocessor")
end)
end)
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