From 11f2201659c98c781cf6530e2a833a0e816ea85f Mon Sep 17 00:00:00 2001 From: Connor Olding Date: Fri, 24 Aug 2018 07:53:14 +0200 Subject: [PATCH] label registers in dumps and reorder debug output --- debug.asm | 159 ++++++++++++++++++++++++++++++++++++++++++++++++----- kernel.asm | 67 +++++++++++----------- 2 files changed, 177 insertions(+), 49 deletions(-) diff --git a/debug.asm b/debug.asm index 9003c4d..2c85b21 100644 --- a/debug.asm +++ b/debug.asm @@ -8,16 +8,21 @@ Drive64Write: // TODO: a0 should be double-word aligned if used directly with DMA // assert a0 (RAM address) is word-aligned andi t9, a0, 3 - bnezl t9, Drive64WriteExit + bnez t9, Drive64WriteExit lli v0, 1 // assert a1 (copy length) is word-aligned andi t9, a1, 3 - bnezl t9, Drive64WriteExit + bnez t9, Drive64WriteExit lli v0, 2 blez a1, Drive64WriteExit // nothing to write? nothing to do! - lli v0, 0 // delay slot + lli v0, 0 + + lui t0, K_BASE + lw t1, K_CONSOLE_AVAILABLE(t0) + beqz t1, Drive64WriteExit + lli v0, 0 lui a2, 0x103F // SDRAM destination move a3, a1 // SDRAM length @@ -28,7 +33,7 @@ Drive64Write: subu t6, a0, t6 // align a0 to data line - cache 1, 0(t6) // data cache Index Writeback Invalidate - addiu t6, 0x10 // (delay slot) += data line size + addiu t6, 0x10 // += data line size sltu at, t6, t7 bnez at,- nop @@ -47,7 +52,7 @@ Drive64Write: sw t1, PI_DRAM_ADDR(t5) sw t2, PI_CART_ADDR(t5) sw t3, PI_RD_LEN(t5) // "read" from DRAM to cart -// PI_WAIT() // if we always wait before doing operations, this shouldn't be necessary + PI_WAIT() Drive64WriteDirect: // TODO: rewrite so this takes a0,a1 instead of a2,a3 lli v0, 0 @@ -102,17 +107,11 @@ DumpAndWrite: or s0, a2, r0 jal xxd or s1, a3, r0 - // v0 passthru - bnez v0, DumpAndWriteExit - lui t0, K_BASE // delay slot - lw t1, K_CONSOLE_AVAILABLE(t0) - beqz t1, DumpAndWriteExit - - ori a0, s0, r0 // delay slot + or a0, s0, r0 // delay slot jal Drive64Write - ori a1, s1, r0 + or a1, s1, r0 // v0 passthru DumpAndWriteExit: @@ -122,6 +121,140 @@ DumpAndWriteExit: jr ra addiu sp, sp, 0x20 +DumpRegisters: + // NOTE: only use this in ISR_Main + // a0: temp string address + // a1: temp string maximum length + // v0: error code (0 is OK) + // TODO: 64-bit variant + subiu sp, 0x30 + sw ra, 0x10(sp) + sw s0, 0x14(sp) + sw s1, 0x18(sp) + sw s2, 0x1C(sp) + sw s3, 0x20(sp) + + slti at, a1, (4 + 8 + 1) * 34 + 1 // = 443 + bnez at, DumpRegistersExit + lli v0, 1 + + la s0, DumpRegistersStrings + lui s1, K_BASE + +macro DumpReg(offset) { + lb t1, 0(s0) + lb t2, 1(s0) + lb t3, 2(s0) + lb t4, 3(s0) + sb t1, 0(a0) + sb t2, 1(a0) + sb t3, 2(a0) + sb t4, 3(a0) + addiu a0, 4 + + jal DumpRegistersHelper // a0 passthru + lw a1, K_DUMP+{offset}+4(s1) + + or a0, v0, r0 +} + + lli s2, 0x20 // ascii space + lli s3, 0x0A // ascii newline + +define DR_i(0) +while {DR_i} < 32 { + DumpReg({DR_i} * 8) + sb s2, 0(a0) + addiu a0, 1 + addiu s0, 16 * 4 + DumpReg({DR_i} * 8 + 0x80) + sb s3, 0(a0) + addiu a0, 1 + subiu s0, 16 * 4 - 4 + evaluate DR_i({DR_i} + 2) +} + + // dump HI and LO separately + addiu s0, 16 * 4 + DumpReg(32 * 8) + sb s2, 0(a0) + addiu a0, 1 + addiu s0, 4 + DumpReg(33 * 8) + sb s3, 0(a0) + addiu a0, 1 + + sb r0, 0(a0) // null-terminate + lli v0, 0 + +DumpRegistersExit: + lw ra, 0x10(sp) + lw s0, 0x14(sp) + lw s1, 0x18(sp) + lw s2, 0x1C(sp) + lw s3, 0x20(sp) + jr ra + addiu sp, 0x20 + +DumpRegistersHelper: + // a0: output pointer + // a1: 32-bit value to dump + // v0: new output pointer + andi t1, a1, 0xF + srl t2, a1, 4 + andi t2, t2, 0xF + srl t3, a1, 8 + andi t3, t3, 0xF + srl t4, a1, 12 + andi t4, t4, 0xF + srl t5, a1, 16 + andi t5, t5, 0xF + srl t6, a1, 20 + andi t6, t6, 0xF + srl t7, a1, 24 + andi t7, t7, 0xF + srl t8, a1, 28 + +macro AsciiNybble(reg, out) { + sltiu at, {reg}, 0xA + bnez at,+ + addiu {out}, {reg}, 0x30 // delay slot + addiu {out}, {reg}, 0x41 - 0xA ++ +} + + AsciiNybble(t8, v0) + sb v0, 0(a0) + AsciiNybble(t7, v0) + sb v0, 1(a0) + AsciiNybble(t6, v0) + sb v0, 2(a0) + AsciiNybble(t5, v0) + sb v0, 3(a0) + AsciiNybble(t4, v0) + sb v0, 4(a0) + AsciiNybble(t3, v0) + sb v0, 5(a0) + AsciiNybble(t2, v0) + sb v0, 6(a0) + AsciiNybble(t1, v0) + sb v0, 7(a0) + + jr ra + addiu v0, a0, 8 + +// each string is assumed to be 4 bytes long +DumpRegistersStrings: +db "r0: ", "at: ", "v0: ", "v1: " +db "a0: ", "a1: ", "a2: ", "a3: " +db "t0: ", "t1: ", "t2: ", "t3: " +db "t4: ", "t5: ", "t6: ", "t7: " +db "s0: ", "s1: ", "s2: ", "s3: " +db "s4: ", "s5: ", "s6: ", "s7: " +db "t8: ", "t9: ", "k0: ", "k1: " +db "gp: ", "sp: ", "fp: ", "ra: " +db "HI: ", "LO: " + PokeDataCache: lui a0, 0x8000 ori a1, a0, 8 * 1024 // cache size diff --git a/kernel.asm b/kernel.asm index b783f79..5bab991 100644 --- a/kernel.asm +++ b/kernel.asm @@ -294,45 +294,9 @@ InterruptHandler: ISR_Main: // free to modify any GPR from here to ISR_Exit -if K_DEBUG { KMaybeDumpString(KS_Newline) KMaybeDumpString(KS_Handling) - - ori a0, k0, K_DUMP + 0x80 * 0 - lli a1, 0x80 - ori a2, k0, K_XXD - jal DumpAndWrite - lli a3, 0x80 * 4 - - KMaybeDumpString(KS_Newline) - - ori a0, k0, K_DUMP + 0x80 * 1 - lli a1, 0x80 - ori a2, k0, K_XXD - jal DumpAndWrite - lli a3, 0x80 * 4 - - KMaybeDumpString(KS_Newline) - - // currently just 0x10 in size: LO and HI registers. - ori a0, k0, K_DUMP + 0x80 * 2 - lli a1, 0x10 - ori a2, k0, K_XXD - jal DumpAndWrite - lli a3, 0x10 * 4 - - KMaybeDumpString(KS_Newline) - KMaybeDumpString(KS_States) - - ori a0, k0, K_REASON - lli a1, 0x80 - ori a2, k0, K_XXD - jal DumpAndWrite - lli a3, 0x80 * 4 - - KMaybeDumpString(KS_Newline) KMaybeDumpString(KS_Code) -} // switch-case on the cause code: // conveniently, the ExcCode in Cause is already shifted left by 2. @@ -344,8 +308,39 @@ if K_DEBUG { jr t4 nop KCodeDone: + +if K_DEBUG { + ori a0, k0, K_XXD + sd r0, 0x1B8(a0) + sd r0, 0x1C0(a0) + sd r0, 0x1C8(a0) + sd r0, 0x1D0(a0) + sd r0, 0x1D8(a0) + sd r0, 0x1E0(a0) + sd r0, 0x1E8(a0) + sd r0, 0x1F0(a0) + sd r0, 0x1F8(a0) + jal DumpRegisters + lli a1, 0x200 + KMaybeDumpString(KS_Newline) + ori a0, k0, K_XXD + jal Drive64Write + lli a1, 0x200 + + KMaybeDumpString(KS_Newline) + KMaybeDumpString(KS_States) + + ori a0, k0, K_REASON + lli a1, 0x80 + ori a2, k0, K_XXD + jal DumpAndWrite + lli a3, 0x80 * 4 + + KMaybeDumpString(KS_Newline) +} + ISR_Exit: sw r0, K_IN_ISR(k0)